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HV:treewide:rename enum vpic_wire_mode, stack_canary, segment_override, pde_index

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For data structure types "enum vpic_wire_mode, struct stack_canary",
its name is identical with variable name in the same scope.
This MISRA C  violation is detected by static analysis tool.
For variables "segment_override, pde_index", its name is identical
with function name. This MISRA C  violation is detected.
Naming convention rule:Variable name can be shortened from
its data structure type name.

The following udpates are made:
enum vpic_wire_mode vpic_wire_mode-->enum vpic_wire_mode wire_mode
struct stack_canary stack_canary-->struct stack_canary stk_canary
uint8_t segment_override:1 --> uint8_t seg_override:1
uint32_t pde_index--> uint32_t pde_idx

V1-->V2:
	Remove update "enum cpu_state cpu_state-->enum cpu_state state"
	and "enum irqstate irqstate-->enum irq_ops_mode ops_mode", other
	patch will cover it.
V2-->V3:
	Update "uint32_t pde_index--> uint32_t pde_idx".

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
This commit is contained in:
Xiangyang Wu 2018-07-30 14:23:38 +08:00 committed by lijinxia
parent 52fe9f419f
commit 6e77a8d5f1
11 changed files with 25 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hypervisor/arch/x86/cpu.c
View File

@ -330,7 +330,7 @@ static uint64_t get_random_value(void)
static void set_fs_base(void)
{
struct stack_canary *psc = &get_cpu_var(stack_canary);
struct stack_canary *psc = &get_cpu_var(stk_canary);
psc->canary = get_random_value();
msr_write(MSR_IA32_FS_BASE, (uint64_t)psc);

8
hypervisor/arch/x86/ept.c
View File

@ -50,7 +50,7 @@ static void free_ept_mem(void *pml4_addr)
void *pte_addr;
uint32_t pml4_index;
uint32_t pdpt_index;
uint32_t pde_index;
uint32_t pde_idx;
if (pml4_addr == NULL) {
ASSERT(false, "EPTP is NULL");
@ -74,10 +74,10 @@ static void free_ept_mem(void *pml4_addr)
continue;
}
for (pde_index = 0U; pde_index < IA32E_NUM_ENTRIES;
pde_index++) {
for (pde_idx = 0U; pde_idx < IA32E_NUM_ENTRIES;
pde_idx++) {
/* Walk from the PD table to the page table */
pte_addr = HPA2HVA(find_next_table(pde_index,
pte_addr = HPA2HVA(find_next_table(pde_idx,
pde_addr));
/* Free page table entry table */

4
hypervisor/arch/x86/guest/instr_emul.c
View File

@ -714,7 +714,7 @@ emulate_movs(struct vcpu *vcpu, __unused uint64_t gpa, struct instr_emul_vie *vi
}
}
seg = (vie->segment_override != 0U) ? (vie->segment_register) : CPU_REG_DS;
seg = (vie->seg_override != 0U) ? (vie->segment_register) : CPU_REG_DS;
error = get_gla(vcpu, vie, paging, opsize, vie->addrsize,
PROT_READ, seg, CPU_REG_RSI, &srcaddr, &fault);
if ((error != 0) || (fault != 0)) {
@ -1791,7 +1791,7 @@ decode_prefixes(struct instr_emul_vie *vie, enum vm_cpu_mode cpu_mode, bool cs_d
} else if (x == 0xF2U) {
vie->repnz_present = 1U;
} else if (segment_override(x, &vie->segment_register)) {
vie->segment_override = 1U;
vie->seg_override = 1U;
} else {
break;
}

2
hypervisor/arch/x86/guest/instr_emul_wrapper.h
View File

@ -163,7 +163,7 @@ struct instr_emul_vie {
repnz_present:1, /* REPNE/REPNZ prefix */
opsize_override:1, /* Operand size override */
addrsize_override:1, /* Address size override */
segment_override:1; /* Segment override */
seg_override:1; /* Segment override */
uint8_t mod:2, /* ModRM byte */
reg:4,

10
hypervisor/arch/x86/guest/vioapic.c
View File

@ -347,11 +347,11 @@ vioapic_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
/* mask -> umask */
if ((last.full & IOAPIC_RTE_INTMASK) != 0UL &&
((new.full & IOAPIC_RTE_INTMASK) == 0UL)) {
if ((vioapic->vm->vpic_wire_mode ==
if ((vioapic->vm->wire_mode ==
VPIC_WIRE_NULL) ||
(vioapic->vm->vpic_wire_mode ==
(vioapic->vm->wire_mode ==
VPIC_WIRE_INTR)) {
vioapic->vm->vpic_wire_mode =
vioapic->vm->wire_mode =
VPIC_WIRE_IOAPIC;
dev_dbg(ACRN_DBG_IOAPIC,
"vpic wire mode -> IOAPIC");
@ -362,9 +362,9 @@ vioapic_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
/* unmask -> mask */
} else if (((last.full & IOAPIC_RTE_INTMASK) == 0UL) &&
(new.full & IOAPIC_RTE_INTMASK) != 0UL) {
if (vioapic->vm->vpic_wire_mode ==
if (vioapic->vm->wire_mode ==
VPIC_WIRE_IOAPIC) {
vioapic->vm->vpic_wire_mode =
vioapic->vm->wire_mode =
VPIC_WIRE_INTR;
dev_dbg(ACRN_DBG_IOAPIC,
"vpic wire mode -> INTR");

14
hypervisor/arch/x86/guest/vlapic.c
View File

@ -611,9 +611,9 @@ vlapic_lvt_write_handler(struct acrn_vlapic *vlapic, uint32_t offset)
/* mask -> unmask: may from every vlapic in the vm */
if (((last & APIC_LVT_M) != 0U) && ((val & APIC_LVT_M) == 0U)) {
if (vlapic->vm->vpic_wire_mode == VPIC_WIRE_INTR ||
vlapic->vm->vpic_wire_mode == VPIC_WIRE_NULL) {
vlapic->vm->vpic_wire_mode = VPIC_WIRE_LAPIC;
if (vlapic->vm->wire_mode == VPIC_WIRE_INTR ||
vlapic->vm->wire_mode == VPIC_WIRE_NULL) {
vlapic->vm->wire_mode = VPIC_WIRE_LAPIC;
dev_dbg(ACRN_DBG_LAPIC,
"vpic wire mode -> LAPIC");
} else {
@ -622,8 +622,8 @@ vlapic_lvt_write_handler(struct acrn_vlapic *vlapic, uint32_t offset)
}
/* unmask -> mask: only from the vlapic LINT0-ExtINT enabled */
} else if (((last & APIC_LVT_M) == 0U) && ((val & APIC_LVT_M) != 0U)) {
if (vlapic->vm->vpic_wire_mode == VPIC_WIRE_LAPIC) {
vlapic->vm->vpic_wire_mode = VPIC_WIRE_NULL;
if (vlapic->vm->wire_mode == VPIC_WIRE_LAPIC) {
vlapic->vm->wire_mode = VPIC_WIRE_NULL;
dev_dbg(ACRN_DBG_LAPIC,
"vpic wire mode -> NULL");
}
@ -1279,8 +1279,8 @@ vlapic_svr_write_handler(struct acrn_vlapic *vlapic)
vlapic_mask_lvts(vlapic);
/* the only one enabled LINT0-ExtINT vlapic disabled */
if (vlapic->vm->vpic_wire_mode == VPIC_WIRE_NULL) {
vlapic->vm->vpic_wire_mode = VPIC_WIRE_INTR;
if (vlapic->vm->wire_mode == VPIC_WIRE_NULL) {
vlapic->vm->wire_mode = VPIC_WIRE_INTR;
dev_dbg(ACRN_DBG_LAPIC,
"vpic wire mode -> INTR");
}

2
hypervisor/arch/x86/guest/vm.c
View File

@ -177,7 +177,7 @@ int create_vm(struct vm_description *vm_desc, struct vm **rtn_vm)
vm->vpic = vpic_init(vm);
/* vpic wire_mode default is INTR */
vm->vpic_wire_mode = VPIC_WIRE_INTR;
vm->wire_mode = VPIC_WIRE_INTR;
/* Allocate full emulated vIOAPIC instance */
vm->arch_vm.virt_ioapic = vioapic_init(vm);

2
hypervisor/arch/x86/guest/vpic.c
View File

@ -231,7 +231,7 @@ static void vpic_notify_intr(struct acrn_vpic *vpic)
* interrupt.
*/
i8259->intr_raised = true;
if (vpic->vm->vpic_wire_mode == VPIC_WIRE_INTR) {
if (vpic->vm->wire_mode == VPIC_WIRE_INTR) {
struct vcpu *vcpu = vcpu_from_vid(vpic->vm, 0U);
ASSERT(vcpu != NULL, "vm%d, vcpu0", vpic->vm->attr.id);

2
hypervisor/arch/x86/pm.c
View File

@ -13,7 +13,7 @@ uint8_t host_enter_s3_success = 1U;
void restore_msrs(void)
{
#ifdef STACK_PROTECTOR
struct stack_canary *psc = &get_cpu_var(stack_canary);
struct stack_canary *psc = &get_cpu_var(stk_canary);
msr_write(MSR_IA32_FS_BASE, (uint64_t)psc);
#endif

2
hypervisor/include/arch/x86/guest/vm.h
View File

@ -134,7 +134,7 @@ struct vm {
enum vm_state state; /* VM state */
void *vuart; /* Virtual UART */
struct acrn_vpic *vpic; /* Virtual PIC */
enum vpic_wire_mode vpic_wire_mode;
enum vpic_wire_mode wire_mode;
struct iommu_domain *iommu; /* iommu domain of this VM */
struct list_head list; /* list of VM */
spinlock_t spinlock; /* Spin-lock used to protect VM modifications */

2
hypervisor/include/arch/x86/per_cpu.h
View File

@ -31,7 +31,7 @@ struct per_cpu_region {
void *vcpu;
void *ever_run_vcpu;
#ifdef STACK_PROTECTOR
struct stack_canary stack_canary;
struct stack_canary stk_canary;
#endif
struct per_cpu_timers cpu_timers;
struct sched_context sched_ctx;