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HV: Logical conjunction needs brackets under /arch/x86/guest
The bracket is required when the level of precedence of the operators is less than 13. Add the bracket to logical conjunctions. The commit applys the rule to the files under hypervisor/arch/x86/guest/* Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
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@@ -129,10 +129,10 @@ vioapic_set_pinstate(struct vioapic *vioapic, uint32_t pin, bool newstate)
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}
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needintr = false;
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if (oldcnt == 0 && newcnt == 1) {
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if ((oldcnt == 0) && (newcnt == 1)) {
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needintr = true;
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dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: asserted", pin);
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} else if (oldcnt == 1 && newcnt == 0) {
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} else if ((oldcnt == 1) && (newcnt == 0)) {
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dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: deasserted", pin);
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} else {
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dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: %s, ignored, acnt %d",
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@@ -337,9 +337,9 @@ vioapic_indirect_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
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changed = last.full ^ new.full;
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/* pin0 from vpic mask/unmask */
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if (pin == 0U && (changed & IOAPIC_RTE_INTMASK) != 0UL) {
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if ((pin == 0U) && ((changed & IOAPIC_RTE_INTMASK) != 0UL)) {
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/* mask -> umask */
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if ((last.full & IOAPIC_RTE_INTMASK) != 0UL &&
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if (((last.full & IOAPIC_RTE_INTMASK) != 0UL) &&
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((new.full & IOAPIC_RTE_INTMASK) == 0UL)) {
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if ((vioapic->vm->wire_mode ==
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VPIC_WIRE_NULL) ||
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@@ -355,7 +355,7 @@ vioapic_indirect_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
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}
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/* unmask -> mask */
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} else if (((last.full & IOAPIC_RTE_INTMASK) == 0UL) &&
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(new.full & IOAPIC_RTE_INTMASK) != 0UL) {
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((new.full & IOAPIC_RTE_INTMASK) != 0UL)) {
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if (vioapic->vm->wire_mode ==
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VPIC_WIRE_IOAPIC) {
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vioapic->vm->wire_mode =
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@@ -395,9 +395,9 @@ vioapic_indirect_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
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* - previous interrupt has been EOIed
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* - pin level is asserted
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*/
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if ((vioapic->rtbl[pin].full & IOAPIC_RTE_INTMASK) ==
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IOAPIC_RTE_INTMCLR &&
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(vioapic->rtbl[pin].full & IOAPIC_RTE_REM_IRR) == 0UL &&
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if (((vioapic->rtbl[pin].full & IOAPIC_RTE_INTMASK) ==
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IOAPIC_RTE_INTMCLR) &&
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((vioapic->rtbl[pin].full & IOAPIC_RTE_REM_IRR) == 0UL) &&
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(vioapic->acnt[pin] > 0)) {
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dev_dbg(ACRN_DBG_IOAPIC,
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"ioapic pin%hhu: asserted at rtbl write, acnt %d",
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@@ -410,9 +410,9 @@ vioapic_indirect_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
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* remap for trigger mode change
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* remap for polarity change
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*/
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if ( (changed & IOAPIC_RTE_INTMASK) != 0UL ||
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(changed & IOAPIC_RTE_TRGRMOD) != 0UL ||
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(changed & IOAPIC_RTE_INTPOL ) != 0UL ) {
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if ( ((changed & IOAPIC_RTE_INTMASK) != 0UL) ||
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((changed & IOAPIC_RTE_TRGRMOD) != 0UL) ||
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((changed & IOAPIC_RTE_INTPOL ) != 0UL) ) {
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/* VM enable intr */
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struct ptdev_intx_info intx;
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@@ -472,7 +472,7 @@ vioapic_process_eoi(struct vm *vm, uint32_t vector)
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uint32_t pin, pincount = vioapic_pincount(vm);
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union ioapic_rte rte;
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if (vector < VECTOR_DYNAMIC_START || vector > NR_MAX_VECTOR) {
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if ((vector < VECTOR_DYNAMIC_START) || (vector > NR_MAX_VECTOR)) {
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pr_err("vioapic_process_eoi: invalid vector %u", vector);
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}
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