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HV: Add CLFLUSHOPT instruction.

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CLFLUSHOPT is used to invalidate from every level of the cache hierarchy
in the cache coherence domain the cache line that contains the linear
address specified with memory operand. If that cache line contains
modified date at any level of the cache hierarchy, that data is written
back to memory.

If the platform does not support CLFLUSHOPT instruction, boot will fail.

Signed-off-by: Jack Ren <jack.ren@intel.com>
Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Yuan Liu 2019-06-13 17:40:05 +08:00 committed by ACRN System Integration
parent d0e0871283
commit 6fd397e82b
3 changed files with 9 additions and 0 deletions
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3
hypervisor/arch/x86/cpu_caps.c
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@ -386,6 +386,9 @@ int32_t detect_hardware_support(void)
} else if (!pcpu_has_cap(X86_FEATURE_MTRR)) { } else if (!pcpu_has_cap(X86_FEATURE_MTRR)) {
pr_fatal("%s, MTRR not supported\n", __func__); pr_fatal("%s, MTRR not supported\n", __func__);
ret = -ENODEV; ret = -ENODEV;
} else if (!pcpu_has_cap(X86_FEATURE_CLFLUSHOPT)) {
pr_fatal("%s, CLFLUSHOPT not supported\n", __func__);
ret = -ENODEV;
} else if (!pcpu_has_cap(X86_FEATURE_PAGE1GB)) { } else if (!pcpu_has_cap(X86_FEATURE_PAGE1GB)) {
pr_fatal("%s, not support 1GB page\n", __func__); pr_fatal("%s, not support 1GB page\n", __func__);
ret = -ENODEV; ret = -ENODEV;

1
hypervisor/include/arch/x86/cpufeatures.h
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@ -76,6 +76,7 @@
#define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5U) + 10U) #define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5U) + 10U)
#define X86_FEATURE_CAT ((FEAT_7_0_EBX << 5U) + 15U) #define X86_FEATURE_CAT ((FEAT_7_0_EBX << 5U) + 15U)
#define X86_FEATURE_SMAP ((FEAT_7_0_EBX << 5U) + 20U) #define X86_FEATURE_SMAP ((FEAT_7_0_EBX << 5U) + 20U)
#define X86_FEATURE_CLFLUSHOPT ((FEAT_7_0_EBX << 5U) + 23U)
/* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/ /* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/
#define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5U) + 26U) #define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5U) + 26U)

5
hypervisor/include/arch/x86/mmu.h
View File

@ -169,6 +169,11 @@ static inline void clflush(volatile void *p)
asm volatile ("clflush (%0)" :: "r"(p)); asm volatile ("clflush (%0)" :: "r"(p));
} }
static inline void clflushopt(volatile void *p)
{
asm volatile ("clflushopt (%0)" :: "r"(p));
}
/* get PDPT address from CR3 vaule in PAE mode */ /* get PDPT address from CR3 vaule in PAE mode */
static inline uint64_t get_pae_pdpt_addr(uint64_t cr3) static inline uint64_t get_pae_pdpt_addr(uint64_t cr3)
{ {