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https://github.com/projectacrn/acrn-hypervisor.git
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acrn-config: support non-contiguous HPA for pre-launched VM
This patch modifies the python scripts in scenario, board and vm-configuration to support, 1. Generation of seperate ve820 for each VM. 2. Ability to configure each VM's HPA from acrn-config UI tool. 3. Non-contiguous HPAs for pre-launched VMs. Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com> Tracked-On: #4195 Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Vijay Dhanraj
wenlingz
@@ -6,12 +6,11 @@
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import sys
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import board_cfg_lib
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FOUR_GBYTE = 4 * 1024 * 1024 * 1024
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LOW_MEM_TO_PCI_HOLE = 0x20000000
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def ve820_per_launch(config, hpa_size):
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def ve820_per_launch(config, hpa_size, hpa2_size):
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"""
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Start to generate board.c
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:param config: it is a file pointer of board information for writing to
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@@ -22,88 +21,137 @@ def ve820_per_launch(config, hpa_size):
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board_name = board_cfg_lib.undline_name(board_name)
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high_mem_hpa_len = 0x0
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low_mem_to_pci_hole_len = '0xA0000000'
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low_mem_to_pci_hole = '0x20000000'
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pci_hole_addr = '0xe0000000'
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pci_hole_len = '0x20000000'
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start_low_hpa = 0x100000
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if (int(hpa_size, 16) <= 512 * 1024 * 1024):
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low_mem_hpa_len = int(hpa_size, 16) - 1 * 1024 * 1024
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else:
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low_mem_hpa_len = 511 * 1024 * 1024
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high_mem_hpa_len = int(hpa_size, 16) - 512 * 1024 * 1024
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low_mem_hpa_len = []
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high_mem_hpa_len = []
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high_mem_hpa2_len = []
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high_mem_hpa2_addr = []
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# pre_launch memroy: mem_size is the ve820 length
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print("#include <e820.h>", file=config)
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print("#include <vm.h>", file=config)
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print("", file=config)
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if (high_mem_hpa_len == 0):
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print("#define VE820_ENTRIES_{}\t{}U".format(board_name, 5), file=config)
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else:
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print("#define VE820_ENTRIES_{}\t{}U".format(board_name, 6), file=config)
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print("static const struct e820_entry ve820_entry[{}] = {{".format(
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"VE820_ENTRIES_{}".format(board_name)), file=config)
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print("\t{\t/* usable RAM under 1MB */", file=config)
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print("\t\t.baseaddr = 0x0UL,", file=config)
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print("\t\t.length = 0xF0000UL,\t\t/* 960KB */", file=config)
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print("\t\t.type = E820_TYPE_RAM", file=config)
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print("\t},", file=config)
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print("", file=config)
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print("\t{\t/* mptable */", file=config)
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print("\t\t.baseaddr = 0xF0000UL,\t\t/* 960KB */", file=config)
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print("\t\t.length = 0x10000UL,\t\t/* 16KB */", file=config)
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print("\t\t.type = E820_TYPE_RESERVED", file=config)
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print("\t},", file=config)
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print("", file=config)
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for i in range(board_cfg_lib.VM_COUNT):
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if (int(hpa_size[i], 16) <= 512 * 1024 * 1024):
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low_mem_hpa_len.append(int(hpa_size[i], 16) - 1 * 1024 * 1024)
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high_mem_hpa_len.append(0)
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else:
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low_mem_hpa_len.append(511 * 1024 * 1024)
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high_mem_hpa_len.append(int(hpa_size[i], 16) - 512 * 1024 * 1024)
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print("\t{\t/* lowmem */", file=config)
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#HPA2 is always allocated in >4G space.
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high_mem_hpa2_len.append(int(hpa2_size[i], 16))
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if (high_mem_hpa_len[i] != 0) and (high_mem_hpa2_len[i] != 0):
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high_mem_hpa2_addr.append(hex(FOUR_GBYTE) + high_mem_hpa_len[i])
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else:
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high_mem_hpa2_addr.append(hex(FOUR_GBYTE))
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print("\t\t.baseaddr = {}UL,\t\t/* 1MB */".format(
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hex(start_low_hpa)), file=config)
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print("\t\t.length = {}UL,\t/* {}MB */".format(
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hex(low_mem_hpa_len), low_mem_hpa_len / 1024 / 1024), file=config)
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if (high_mem_hpa_len[i] != 0) and (high_mem_hpa2_len[i] != 0):
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print("#define VM{}_VE820_ENTRIES_{}\t{}U".format(i, board_name, 7), file=config)
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elif (high_mem_hpa_len[i] != 0) or (high_mem_hpa2_len[i] != 0):
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print("#define VM{}_VE820_ENTRIES_{}\t{}U".format(i, board_name, 6), file=config)
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else:
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print("#define VM{}_VE820_ENTRIES_{}\t{}U".format(i, board_name, 5), file=config)
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print("\t\t.type = E820_TYPE_RAM", file=config)
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print("\t},", file=config)
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print("", file=config)
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for i in range(board_cfg_lib.VM_COUNT):
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print("static const struct e820_entry vm{}_ve820_entry[{}] = {{".format(
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i, "VM{}_VE820_ENTRIES_{}".format(i, board_name)), file=config)
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print("\t{\t/* usable RAM under 1MB */", file=config)
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print("\t\t.baseaddr = 0x0UL,", file=config)
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print("\t\t.length = 0xF0000UL,\t\t/* 960KB */", file=config)
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print("\t\t.type = E820_TYPE_RAM", file=config)
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print("\t},", file=config)
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print("", file=config)
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print("\t{\t/* mptable */", file=config)
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print("\t\t.baseaddr = 0xF0000UL,\t\t/* 960KB */", file=config)
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print("\t\t.length = 0x10000UL,\t\t/* 64KB */", file=config)
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print("\t\t.type = E820_TYPE_RESERVED", file=config)
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print("\t},", file=config)
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print("", file=config)
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print("\t{\t/* between lowmem and PCI hole */", file=config)
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print("\t\t.baseaddr = {}UL,\t/* {}MB */".format(
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low_mem_to_pci_hole, int(low_mem_to_pci_hole, 16) / 1024 / 1024), file=config)
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print("\t\t.length = {}UL,\t/* {}MB */".format(
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low_mem_to_pci_hole_len, int(low_mem_to_pci_hole_len, 16) / 1024 / 1024), file=config)
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print("\t\t.type = E820_TYPE_RESERVED", file=config)
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print("\t},", file=config)
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print("", file=config)
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print("\t{\t/* between PCI hole and 4 GB */", file=config)
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print("\t\t.baseaddr = {}UL,\t/* {}GB */".format(
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hex(int(pci_hole_addr, 16)), int(pci_hole_addr, 16) / 1024 / 1024 / 1024), file=config)
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print("\t\t.length = {}UL,\t/* {}MB */".format(
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hex(int(pci_hole_len, 16)), int(pci_hole_len, 16) / 1024 / 1024), file=config)
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print("\t\t.type = E820_TYPE_RESERVED", file=config)
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print("\t},", file=config)
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print("", file=config)
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if (high_mem_hpa_len != 0):
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print("\t{\t/* high mem after 4GB*/", file=config)
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print("\t\t.baseaddr = {}UL,\t/* 4 GB */".format(
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hex(FOUR_GBYTE)), file=config)
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print("\t{\t/* lowmem */", file=config)
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print("\t\t.baseaddr = {}UL,\t\t/* 1MB */".format(
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hex(start_low_hpa)), file=config)
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print("\t\t.length = {}UL,\t/* {}MB */".format(
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hex(high_mem_hpa_len), high_mem_hpa_len / 1024 / 1024), file=config)
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hex(low_mem_hpa_len[i]), low_mem_hpa_len[i] / 1024 / 1024), file=config)
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print("\t\t.type = E820_TYPE_RAM", file=config)
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print("\t},", file=config)
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print("", file=config)
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print("};", file=config)
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print("", file=config)
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print("\t{\t/* between lowmem and PCI hole */", file=config)
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print("\t\t.baseaddr = {}UL,\t/* {}MB */".format(
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low_mem_to_pci_hole, int(low_mem_to_pci_hole, 16) / 1024 / 1024), file=config)
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print("\t\t.length = {}UL,\t/* {}MB */".format(
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low_mem_to_pci_hole_len, int(low_mem_to_pci_hole_len, 16) / 1024 / 1024), file=config)
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print("\t\t.type = E820_TYPE_RESERVED", file=config)
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print("\t},", file=config)
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print("", file=config)
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print("\t{\t/* between PCI hole and 4 GB */", file=config)
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print("\t\t.baseaddr = {}UL,\t/* {}GB */".format(
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hex(int(pci_hole_addr, 16)), int(pci_hole_addr, 16) / 1024 / 1024 / 1024), file=config)
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print("\t\t.length = {}UL,\t/* {}MB */".format(
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hex(int(pci_hole_len, 16)), int(pci_hole_len, 16) / 1024 / 1024), file=config)
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print("\t\t.type = E820_TYPE_RESERVED", file=config)
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print("\t},", file=config)
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print("", file=config)
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if (high_mem_hpa_len[i] != 0) and (high_mem_hpa2_len[i] != 0):
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print("\t{\t/* high mem after 4GB*/", file=config)
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print("\t\t.baseaddr = {}UL,\t/* 4 GB */".format(
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hex(FOUR_GBYTE)), file=config)
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print("\t\t.length = {}UL,\t/* {}MB */".format(
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hex(high_mem_hpa_len[i]), high_mem_hpa_len[i] / 1024 / 1024), file=config)
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print("\t\t.type = E820_TYPE_RAM", file=config)
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print("\t},", file=config)
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print("", file=config)
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print("\t{\t/* HPA2 after high mem*/", file=config)
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print("\t\t.baseaddr = {}UL,\t/* {}GB */".format(
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hex(high_mem_hpa2_addr[i]), int(high_mem_hpa2_addr[i], 16) / 1024 / 1024 / 1024), file=config)
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print("\t\t.length = {}UL,\t/* {}MB */".format(
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hex(high_mem_hpa_len[i]), high_mem_hpa_len[i] / 1024 / 1024), file=config)
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print("\t\t.type = E820_TYPE_RAM", file=config)
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print("\t},", file=config)
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print("", file=config)
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elif (high_mem_hpa_len[i] != 0):
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print("\t{\t/* high mem after 4GB*/", file=config)
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print("\t\t.baseaddr = {}UL,\t/* 4 GB */".format(
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hex(FOUR_GBYTE)), file=config)
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print("\t\t.length = {}UL,\t/* {}MB */".format(
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hex(high_mem_hpa_len[i]), high_mem_hpa_len[i] / 1024 / 1024), file=config)
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print("\t\t.type = E820_TYPE_RAM", file=config)
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print("\t},", file=config)
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print("", file=config)
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elif(high_mem_hpa2_len[i] != 0):
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print("\t{\t/* HPA2 after 4GB*/", file=config)
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print("\t\t.baseaddr = {}UL,\t/* 4 GB */".format(
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hex(FOUR_GBYTE)), file=config)
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print("\t\t.length = {}UL,\t/* {}MB */".format(
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hex(high_mem_hpa2_len[i]), high_mem_hpa2_len[i] / 1024 / 1024), file=config)
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print("\t\t.type = E820_TYPE_RAM", file=config)
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print("\t},", file=config)
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print("", file=config)
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print("};", file=config)
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print("", file=config)
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print("/**", file=config)
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print(" * @pre vm != NULL", file=config)
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print("*/", file=config)
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print("void create_prelaunched_vm_e820(struct acrn_vm *vm)", file=config)
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print("{", file=config)
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print("\tvm->e820_entry_num = VE820_ENTRIES_{};".format(board_name), file=config)
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print("\tvm->e820_entries = ve820_entry;", file=config)
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for i in range(board_cfg_lib.VM_COUNT):
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print("\tif (vm->vm_id == {}U)".format(hex(i)), file=config)
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print("\t{", file=config)
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print("\t\tvm->e820_entry_num = VM{}_VE820_ENTRIES_{};".format(i, board_name), file=config)
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print("\t\tvm->e820_entries = vm{}_ve820_entry;".format(i), file=config)
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print("\t}", file=config)
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print("", file=config)
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print("}", file=config)
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return err_dic
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@@ -144,9 +192,24 @@ def generate_file(config):
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err_dic['board config: generate ve820.c failed'] = "Unknow type of host physical address size"
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return err_dic
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hpa_size = hpa_size_list[0]
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if pre_vm_cnt != 0 and ('0x' in hpa_size or '0X' in hpa_size):
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err_dic = ve820_per_launch(config, hpa_size)
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# read HPA2 mem size from scenario.xml
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hpa2_size_list = board_cfg_lib.get_sub_leaf_tag(
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board_cfg_lib.SCENARIO_INFO_FILE, "memory", "size_hpa2")
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ret = board_cfg_lib.is_hpa_size(hpa2_size_list)
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if not ret:
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board_cfg_lib.print_red("Unknow type of second host physical address size", err=True)
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err_dic['board config: generate ve820.c failed'] = "Unknow type of second host physical address size"
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return err_dic
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# HPA size for both VMs should have valid length.
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for i in range(board_cfg_lib.VM_COUNT):
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if hpa_size_list[i] == '0x0' or hpa_size_list[i] == '0X0':
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board_cfg_lib.print_red("HPA size should not be zero", err=True)
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err_dic['board config: generate ve820.c failed'] = "HPA size should not be zero"
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return err_dic
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if pre_vm_cnt != 0:
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err_dic = ve820_per_launch(config, hpa_size_list, hpa2_size_list)
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else:
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non_ve820_pre_launch(config)
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