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HV: trap and validate px request

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Currently acrn partitions cpus between SOS and UOS, so the default
policy is to allow guest managing CPU px state. However we would
not blindly passthrough perf_ctrl MSR to guest. Instead guest access
is always trapped and validated by acrn hypervisor before forwarding
to pcpu. Doing so leaves room for future power budget control in
hypervisor, e.g. limiting turbo percentage that a cpu can enter.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
This commit is contained in:
Victor Sun
2018-04-05 19:08:38 +08:00
committed by Jack Ren
parent 1d0d4d3185
commit 7647517a15
3 changed files with 42 additions and 0 deletions
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16
hypervisor/arch/x86/guest/vmsr.c
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@@ -33,6 +33,7 @@
#include <hv_arch.h>
#include <hv_debug.h>
#include <ucode.h>
#include <cpu_state_tbl.h>
/*MRS need to be emulated, the order in this array better as freq of ops*/
static const uint32_t emulated_msrs[] = {
@@ -135,6 +136,8 @@ void init_msr_emulation(struct vcpu *vcpu)
for (i = 0; i < msrs_count; i++)
enable_msr_interception(msr_bitmap, emulated_msrs[i]);
enable_msr_interception(msr_bitmap, MSR_IA32_PERF_CTL);
/* below MSR protected from guest OS, if access to inject gp*/
enable_msr_interception(msr_bitmap, MSR_IA32_MTRR_CAP);
enable_msr_interception(msr_bitmap, MSR_IA32_MTRR_DEF_TYPE);
@@ -207,6 +210,11 @@ int rdmsr_handler(struct vcpu *vcpu)
v = get_microcode_version();
break;
}
case MSR_IA32_PERF_CTL:
{
v = msr_read(msr);
break;
}
/* following MSR not emulated now just left for future */
case MSR_IA32_SYSENTER_CS:
@@ -303,6 +311,14 @@ int wrmsr_handler(struct vcpu *vcpu)
acrn_update_ucode(vcpu, v);
break;
}
case MSR_IA32_PERF_CTL:
{
if (validate_pstate(vcpu->vm, v)) {
break;
}
msr_write(msr, v);
break;
}
/* following MSR not emulated now just left for future */
case MSR_IA32_SYSENTER_CS: