Project ACRN hypervisor
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Victor Sun 7647517a15 HV: trap and validate px request
Currently acrn partitions cpus between SOS and UOS, so the default
policy is to allow guest managing CPU px state. However we would
not blindly passthrough perf_ctrl MSR to guest. Instead guest access
is always trapped and validated by acrn hypervisor before forwarding
to pcpu. Doing so leaves room for future power budget control in
hypervisor, e.g. limiting turbo percentage that a cpu can enter.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
devicemodel DM: build UOS DSDT with vcpu px state data 2018-05-15 17:25:25 +08:00
doc getting_started: update dependency for Fedora 27 2018-05-15 17:19:37 +08:00
hypervisor HV: trap and validate px request 2018-05-15 17:25:25 +08:00