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hv: emulate MSR_PLATFORM_INFO (17h)

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This patch emulates the PLATFORM_INFO MSR in hypervisor to make it
only visible to Service VM, and only processor ratios (bit 15:8,
47:40 and 55:48) and sample part bit (27) are exponsed. This is
intended to prevent Service VM from changing processor parameters
like turbo ratio.

Tracked-On: 
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
This commit is contained in:
Jiaqing Zhao 2023-05-19 07:37:15 +00:00 committed by acrnsi-robot
parent 5ed6190741
commit 770cf8c434
3 changed files with 22 additions and 1 deletions
hypervisor
arch/x86/guest
vmsr.c
include/arch/x86/asm
guest
vcpu.h
msr.h

15
hypervisor/arch/x86/guest/vmsr.c
View File

@ -77,6 +77,8 @@ static uint32_t emulated_guest_msrs[NUM_EMULATED_MSRS] = {
MSR_TEST_CTL,
MSR_PLATFORM_INFO,
/* VMX: CPUID.01H.ECX[5] */
#ifdef CONFIG_NVMX_ENABLED
LIST_OF_VMX_MSRS,
@ -770,6 +772,19 @@ int32_t rdmsr_vmexit_handler(struct acrn_vcpu *vcpu)
}
break;
}
case MSR_PLATFORM_INFO:
{
if (is_service_vm(vcpu->vm)) {
v = msr_read(msr);
v &= MSR_PLATFORM_INFO_MAX_NON_TURBO_LIM_RATIO_MASK |
MSR_PLATFORM_INFO_MAX_EFFICIENCY_RATIO_MASK |
MSR_PLATFORM_INFO_MIN_OPERATING_RATIO_MASK |
MSR_PLATFORM_INFO_SAMPLE_PART;
} else {
err = -EACCES;
}
break;
}
#ifdef CONFIG_VCAT_ENABLED
case MSR_IA32_L2_MASK_BASE ... (MSR_IA32_L2_MASK_BASE + NUM_CAT_L2_MSRS - 1U):
case MSR_IA32_L3_MASK_BASE ... (MSR_IA32_L3_MASK_BASE + NUM_CAT_L3_MSRS - 1U):

2
hypervisor/include/arch/x86/asm/guest/vcpu.h
View File

@ -175,7 +175,7 @@ enum reset_mode;
#define SECURE_WORLD 1
#define NUM_WORLD_MSRS 2U
#define NUM_COMMON_MSRS 24U
#define NUM_COMMON_MSRS 25U
#ifdef CONFIG_VCAT_ENABLED
#define NUM_CAT_L2_MSRS MAX_CACHE_CLOS_NUM_ENTRIES

6
hypervisor/include/arch/x86/asm/msr.h
View File

@ -673,4 +673,10 @@ void update_msr_bitmap_x2apic_passthru(struct acrn_vcpu *vcpu);
/* Flush L1 D-cache */
#define IA32_L1D_FLUSH (1UL << 0U)
/* PLATFORM INFO bits */
#define MSR_PLATFORM_INFO_MAX_NON_TURBO_LIM_RATIO_MASK (0x000000000000ff00UL) /* 15:8 */
#define MSR_PLATFORM_INFO_MAX_EFFICIENCY_RATIO_MASK (0x0000ff0000000000UL) /* 47:40 */
#define MSR_PLATFORM_INFO_MIN_OPERATING_RATIO_MASK (0x00ff000000000000UL) /* 55:48 */
#define MSR_PLATFORM_INFO_SAMPLE_PART (1UL << 27U)
#endif /* MSR_H */