github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-06-22 13:37:10 +00:00
Code Issues Projects Releases Wiki Activity

hv: virq: refine hypervisor/arch/x86/virq.c

Browse Source 
The MISRA-C Standards suggests use brackets to clarify the precedence
order of logical conjunctions.

Tracked-On: #861
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
This commit is contained in:
yuhong.tao@intel.com 2018-12-29 11:31:45 +00:00 committed by wenlingz
parent 7ebc4877c8
commit 7a930d8833
1 changed files with 4 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
hypervisor/arch/x86/virq.c
View File

@ -131,7 +131,7 @@ static int32_t vcpu_inject_vlapic_int(struct acrn_vcpu *vcpu)
* through the local APIC.
*/
if (!(vector >= 16U && vector <= 255U)) {
if (!((vector >= 16U) && (vector <= 255U))) {
dev_dbg(ACRN_DBG_INTR, "invalid vector %d from local APIC", vector);
ret = -1;
} else {
@ -204,15 +204,12 @@ int32_t vcpu_queue_exception(struct acrn_vcpu *vcpu, uint32_t vector, uint32_t e
* double fault */
prev_class = get_excep_class(prev_vector);
new_class = get_excep_class(vector);
if (prev_vector == IDT_DF &&
new_class != EXCEPTION_CLASS_BENIGN) {
if ((prev_vector == IDT_DF) && (new_class != EXCEPTION_CLASS_BENIGN)) {
/* triple fault happen - shutdwon mode */
vcpu_make_request(vcpu, ACRN_REQUEST_TRP_FAULT);
return 0;
} else if ((prev_class == EXCEPTION_CLASS_CONT &&
new_class == EXCEPTION_CLASS_CONT) ||
(prev_class == EXCEPTION_CLASS_PF &&
new_class != EXCEPTION_CLASS_BENIGN)) {
} else if (((prev_class == EXCEPTION_CLASS_CONT) && (new_class == EXCEPTION_CLASS_CONT)) ||
((prev_class == EXCEPTION_CLASS_PF) && (new_class != EXCEPTION_CLASS_BENIGN))) {
/* generate double fault */
vector = IDT_DF;
err_code = 0U;