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hv: virq: refine hypervisor/arch/x86/virq.c
The MISRA-C Standards suggests use brackets to clarify the precedence order of logical conjunctions. Tracked-On: #861 Acked-by: Eddie Dong <eddie.dong@intel.com> Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
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@ -131,7 +131,7 @@ static int32_t vcpu_inject_vlapic_int(struct acrn_vcpu *vcpu)
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* through the local APIC.
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*/
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if (!(vector >= 16U && vector <= 255U)) {
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if (!((vector >= 16U) && (vector <= 255U))) {
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dev_dbg(ACRN_DBG_INTR, "invalid vector %d from local APIC", vector);
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ret = -1;
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} else {
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@ -204,15 +204,12 @@ int32_t vcpu_queue_exception(struct acrn_vcpu *vcpu, uint32_t vector, uint32_t e
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* double fault */
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prev_class = get_excep_class(prev_vector);
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new_class = get_excep_class(vector);
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if (prev_vector == IDT_DF &&
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new_class != EXCEPTION_CLASS_BENIGN) {
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if ((prev_vector == IDT_DF) && (new_class != EXCEPTION_CLASS_BENIGN)) {
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/* triple fault happen - shutdwon mode */
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vcpu_make_request(vcpu, ACRN_REQUEST_TRP_FAULT);
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return 0;
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} else if ((prev_class == EXCEPTION_CLASS_CONT &&
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new_class == EXCEPTION_CLASS_CONT) ||
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(prev_class == EXCEPTION_CLASS_PF &&
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new_class != EXCEPTION_CLASS_BENIGN)) {
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} else if (((prev_class == EXCEPTION_CLASS_CONT) && (new_class == EXCEPTION_CLASS_CONT)) ||
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((prev_class == EXCEPTION_CLASS_PF) && (new_class != EXCEPTION_CLASS_BENIGN))) {
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/* generate double fault */
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vector = IDT_DF;
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err_code = 0U;
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