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https://github.com/projectacrn/acrn-hypervisor.git
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Revert "hv: trap vm0 write/read pm1a/pm1b registers"
This reverts commit 711cff0251
.
This commit is contained in:
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0648f01e55
commit
7ab3c2a1ac
@ -121,98 +121,3 @@ int vm_load_pm_s_state(struct vm *vm)
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return -1;
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}
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}
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static inline uint16_t s3_enabled(uint16_t pm1_cnt)
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{
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return pm1_cnt & (1 << BIT_SLP_EN);
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}
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static inline uint8_t get_slp_typx(uint16_t pm1_cnt)
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{
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return (pm1_cnt & 0x1fff) >> BIT_SLP_TYPx;
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}
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static uint32_t pm1ab_io_read(__unused struct vm_io_handler *hdlr,
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__unused struct vm *vm, uint16_t addr, size_t width)
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{
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uint32_t val = io_read(addr, width);
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if (host_enter_s3_success == 0) {
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/* If host S3 enter failes, we should set BIT_WAK_STS
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* bit for vm0 and let vm0 back from S3 failure path.
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*/
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if (addr == vm->pm.sx_state_data->pm1a_evt.address) {
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val |= (1 << BIT_WAK_STS);
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}
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}
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return val;
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}
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static void pm1ab_io_write(__unused struct vm_io_handler *hdlr,
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__unused struct vm *vm, uint16_t addr, size_t width,
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uint32_t v)
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{
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static uint32_t pm1a_cnt_ready = 0;
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if (width == 2) {
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uint8_t val = get_slp_typx(v);
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if ((addr == vm->pm.sx_state_data->pm1a_cnt.address)
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&& (val == vm->pm.sx_state_data->s3_pkg.val_pm1a)
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&& s3_enabled(v)) {
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if (vm->pm.sx_state_data->pm1b_cnt.address) {
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pm1a_cnt_ready = v;
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} else {
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enter_s3(vm, v, 0);
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}
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return;
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}
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if ((addr == vm->pm.sx_state_data->pm1b_cnt.address)
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&& (val == vm->pm.sx_state_data->s3_pkg.val_pm1b)
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&& s3_enabled(v)) {
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if (pm1a_cnt_ready) {
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enter_s3(vm, pm1a_cnt_ready, v);
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pm1a_cnt_ready = 0;
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} else {
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/* the case broke ACPI spec */
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pr_err("PM1B_CNT write error!");
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}
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return;
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}
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}
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io_write(v, addr, width);
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}
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void register_gas_io_handler(struct vm *vm, struct acpi_generic_address *gas)
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{
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uint8_t io_len[5] = {0, 1, 2, 4, 8};
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struct vm_io_range gas_io;
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if ((gas->address == 0)
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|| (gas->space_id != SPACE_SYSTEM_IO)
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|| (gas->access_size == 0)
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|| (gas->access_size > 4))
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return;
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gas_io.flags = IO_ATTR_RW,
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gas_io.base = gas->address,
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gas_io.len = io_len[gas->access_size];
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register_io_emulation_handler(vm, &gas_io,
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&pm1ab_io_read, &pm1ab_io_write);
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pr_dbg("Enable PM1A trap for VM %d, port 0x%x, size %d\n",
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vm->attr.id, gas_io.base, gas_io.len);
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}
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void register_pm1ab_handler(struct vm *vm)
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{
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register_gas_io_handler(vm, &vm->pm.sx_state_data->pm1a_evt);
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register_gas_io_handler(vm, &vm->pm.sx_state_data->pm1b_evt);
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register_gas_io_handler(vm, &vm->pm.sx_state_data->pm1a_cnt);
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register_gas_io_handler(vm, &vm->pm.sx_state_data->pm1b_cnt);
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}
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@ -143,8 +143,7 @@ int create_vm(struct vm_description *vm_desc, struct vm **rtn_vm)
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if (is_vm0(vm)) {
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/* Load pm S state data */
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if (vm_load_pm_s_state(vm) == 0)
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register_pm1ab_handler(vm);
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vm_load_pm_s_state(vm);
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/* Create virtual uart */
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vm->vuart = vuart_init(vm);
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@ -6,9 +6,6 @@
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struct run_context cpu_ctx;
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/* whether the host enter s3 success */
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uint8_t host_enter_s3_success = 1;
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void restore_msrs(void)
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{
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#ifdef STACK_PROTECTOR
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@ -74,16 +71,12 @@ int enter_s3(struct vm *vm, uint32_t pm1a_cnt_val,
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uint32_t pm1b_cnt_val)
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{
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uint32_t pcpu_id;
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int ret;
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uint64_t pmain_entry_saved;
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uint32_t guest_wakeup_vec32;
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uint64_t *pmain_entry;
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/* We assume enter s3 success by default */
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host_enter_s3_success = 1;
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if (vm->pm.sx_state_data == NULL) {
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pr_err("No Sx state info avaiable. No Sx support");
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host_enter_s3_success = 0;
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return -1;
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}
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@ -11,6 +11,5 @@ void vm_setup_cpu_state(struct vm *vm);
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int vm_load_pm_s_state(struct vm *vm);
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int validate_pstate(struct vm *vm, uint64_t perf_ctl);
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struct cpu_cx_data* get_target_cx(struct vm *vm, uint8_t cn);
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void register_pm1ab_handler(struct vm *vm);
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#endif /* PM_H */
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@ -5,12 +5,8 @@
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#ifndef HOST_PM_H
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#define BIT_SLP_TYPx 10U
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#define BIT_SLP_EN 13U
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#define BIT_WAK_STS 15U
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extern uint8_t host_enter_s3_success;
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int enter_s3(struct vm *vm, uint32_t pm1a_cnt_val,
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uint32_t pm1b_cnt_val);
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extern void __enter_s3(struct vm *vm, uint32_t pm1a_cnt_val,
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