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https://github.com/projectacrn/acrn-hypervisor.git
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hv: implement msix.c for MSI-X remapping
Similar to MSI emulation, this patch emulates the Message Control word within MSI-X Capability Structure. Also it emulates MSI-X table. MSI-X remapping is triggered when the guest is changing the Mask bit in Vector Control, or the Message Data/Addr when MSI-X Enable bit is set. Tracked-On: #1568 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Zide Chen
lijinxia
parent
dcebdb8e98
commit
7c506ebc69
@ -200,3 +200,8 @@ config IOMMU_INIT_BUS_LIMIT
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hex "bus limitation when iommu init"
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hex "bus limitation when iommu init"
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default 0xf if PLATFORM_SBL
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default 0xf if PLATFORM_SBL
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default 0xff if PLATFORM_UEFI
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default 0xff if PLATFORM_UEFI
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config MAX_MSIX_TABLE_NUM
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int "Maximum number of MSI-X Table per device"
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range 1 2048
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default 16
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357
hypervisor/dm/vpci/msix.c
Normal file
357
hypervisor/dm/vpci/msix.c
Normal file
@ -0,0 +1,357 @@
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/*
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <hypervisor.h>
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#include "pci_priv.h"
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static inline bool msixcap_access(struct pci_vdev *vdev, uint32_t offset)
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{
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if (vdev->msix.capoff == 0U) {
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return 0;
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}
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return in_range(offset, vdev->msix.capoff, vdev->msix.caplen);
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}
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static inline bool msixtable_access(struct pci_vdev *vdev, uint32_t offset)
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{
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return in_range(offset, vdev->msix.table_offset, vdev->msix.table_count * MSIX_TABLE_ENTRY_SIZE);
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}
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static int vmsix_remap_entry(struct pci_vdev *vdev, uint32_t index, bool enable)
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{
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struct msix_table_entry *pentry;
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struct ptdev_msi_info info;
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uint64_t hva;
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int ret;
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info.is_msix = 1;
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info.vmsi_addr = vdev->msix.tables[index].addr;
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info.vmsi_data = (enable) ? vdev->msix.tables[index].data : 0U;
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ret = ptdev_msix_remap(vdev->vpci->vm, vdev->vbdf.value, index, &info);
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if (ret != 0) {
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return ret;
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}
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/* Write the table entry to the physical structure */
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hva = vdev->msix.mmio_hva + vdev->msix.table_offset;
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pentry = (struct msix_table_entry *)hva + index;
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pentry->addr = info.pmsi_addr;
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pentry->data = info.pmsi_data;
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pentry->vector_control = vdev->msix.tables[index].vector_control;
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return ret;
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}
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static inline void enable_disable_msix(struct pci_vdev *vdev, bool enable)
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{
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uint32_t msgctrl;
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msgctrl = pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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if (enable) {
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msgctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
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} else {
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msgctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
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}
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pci_pdev_write_cfg(vdev->pdev.bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U, msgctrl);
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}
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/* Do MSI-X remap for all MSI-X table entries in the target device */
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static int vmsix_remap(struct pci_vdev *vdev, bool enable)
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{
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uint32_t index;
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int ret;
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/* disable MSI-X during configuration */
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enable_disable_msix(vdev, false);
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for (index = 0U; index < vdev->msix.table_count; index++) {
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ret = vmsix_remap_entry(vdev, index, enable);
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if (ret != 0) {
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return ret;
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}
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}
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/* If MSI Enable is being set, make sure INTxDIS bit is set */
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if (enable) {
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enable_disable_pci_intx(vdev->pdev.bdf, false);
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}
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enable_disable_msix(vdev, enable);
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return 0;
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}
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/* Do MSI-X remap for one MSI-X table entry only */
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static int vmsix_remap_one_entry(struct pci_vdev *vdev, uint32_t index, bool enable)
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{
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uint32_t msgctrl;
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int ret;
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/* disable MSI-X during configuration */
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enable_disable_msix(vdev, false);
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ret = vmsix_remap_entry(vdev, index, enable);
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if (ret != 0) {
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return ret;
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}
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/* If MSI Enable is being set, make sure INTxDIS bit is set */
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if (enable) {
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enable_disable_pci_intx(vdev->pdev.bdf, false);
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}
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/* Restore MSI-X Enable bit */
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msgctrl = pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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if ((msgctrl & PCIM_MSIXCTRL_MSIX_ENABLE) == PCIM_MSIXCTRL_MSIX_ENABLE) {
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pci_pdev_write_cfg(vdev->pdev.bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U, msgctrl);
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}
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return ret;
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}
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static int vmsix_cfgread(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val)
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{
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/* For PIO access, we emulate Capability Structures only */
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if (msixcap_access(vdev, offset)) {
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*val = pci_vdev_read_cfg(vdev, offset, bytes);
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return 0;
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}
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return -ENODEV;
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}
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static int vmsix_cfgwrite(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val)
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{
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uint32_t msgctrl;
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/* Writing MSI-X Capability Structure */
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if (msixcap_access(vdev, offset)) {
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msgctrl = pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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/* Write to vdev */
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pci_vdev_write_cfg(vdev, offset, bytes, val);
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/* Writing Message Control field? */
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if ((offset - vdev->msix.capoff) == PCIR_MSIX_CTRL) {
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if (((msgctrl ^ val) & PCIM_MSIXCTRL_MSIX_ENABLE) != 0U) {
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if (val & PCIM_MSIXCTRL_MSIX_ENABLE) {
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(void)vmsix_remap(vdev, true);
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} else {
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(void)vmsix_remap(vdev, false);
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}
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}
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if (((msgctrl ^ val) & PCIM_MSIXCTRL_FUNCTION_MASK) != 0U) {
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pci_pdev_write_cfg(vdev->pdev.bdf, offset, 2U, msgctrl);
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}
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}
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return 0;
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}
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return -ENODEV;
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}
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static void vmsix_table_rw(struct pci_vdev *vdev, struct mmio_request *mmio, uint32_t offset)
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{
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struct msix_table_entry *entry;
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uint32_t vector_control, entry_offset, index;
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bool message_changed = false;
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bool unmasked;
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/* Find out which entry it's accessing */
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offset -= vdev->msix.table_offset;
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index = offset / MSIX_TABLE_ENTRY_SIZE;
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if (index >= vdev->msix.table_count) {
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pr_err("%s, invalid arguments %llx - %llx", __func__, mmio->value, mmio->address);
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return;
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}
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entry = &vdev->msix.tables[index];
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entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
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if (mmio->direction == REQUEST_READ) {
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(void)memcpy_s(&mmio->value, (size_t)mmio->size, (void *)entry + entry_offset, (size_t)mmio->size);
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} else {
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/* Only DWORD and QWORD are permitted */
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if ((mmio->size != 4U) && (mmio->size != 8U)) {
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pr_err("%s, Only DWORD and QWORD are permitted", __func__);
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return;
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}
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/* Save for comparison */
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vector_control = entry->vector_control;
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/* Writing different value to Message Data/Addr? */
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if (((offsetof(struct msix_table_entry, addr) == entry_offset) && (entry->addr != mmio->value)) ||
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((offsetof(struct msix_table_entry, data) == entry_offset) && (entry->data != (uint32_t)mmio->value))) {
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message_changed = true;
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}
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/* Write to pci_vdev */
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(void)memcpy_s((void *)entry + entry_offset, (size_t)mmio->size, &mmio->value, (size_t)mmio->size);
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/* If MSI-X hasn't been enabled, do nothing */
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if ((pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U) & PCIM_MSIXCTRL_MSIX_ENABLE)
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== PCIM_MSIXCTRL_MSIX_ENABLE) {
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if ((((entry->vector_control ^ vector_control) & PCIM_MSIX_VCTRL_MASK) != 0U) || message_changed) {
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unmasked = ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0U);
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(void)vmsix_remap_one_entry(vdev, index, unmasked);
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}
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}
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}
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}
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static int vmsix_table_mmio_access_handler(struct io_request *io_req, void *handler_private_data)
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{
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struct mmio_request *mmio = &io_req->reqs.mmio;
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struct pci_vdev *vdev;
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uint32_t offset;
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uint64_t hva;
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vdev = (struct pci_vdev *)handler_private_data;
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offset = (uint32_t)(mmio->address - vdev->msix.mmio_gpa);
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if (msixtable_access(vdev, offset)) {
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vmsix_table_rw(vdev, mmio, offset);
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} else {
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hva = vdev->msix.mmio_hva + offset;
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/* MSI-X PBA and Capability Table could be in the same range */
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if (mmio->direction == REQUEST_READ) {
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(void)memcpy_s(&mmio->value, (size_t)mmio->size, (const void *)hva, (size_t)mmio->size);
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} else {
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(void)memcpy_s((void *)hva, (size_t)mmio->size, &mmio->value, (size_t)mmio->size);
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}
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}
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return 0;
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}
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static void decode_msix_table_bar(struct pci_vdev *vdev)
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{
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uint32_t bir = vdev->msix.table_bar;
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union pci_bdf pbdf = vdev->pdev.bdf;
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uint64_t base, size;
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uint32_t bar_lo, bar_hi;
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bar_lo = pci_pdev_read_cfg(pbdf, pci_bar_offset(bir), 4U);
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if ((bar_lo & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) {
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/* I/O bar, should never happen */
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pr_err("PCI device (%x) has MSI-X Table at IO BAR", vdev->vbdf.value);
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return;
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}
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/* Get the base address */
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base = (uint64_t)(bar_lo & PCIM_BAR_MEM_BASE);
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if ((bar_lo & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64) {
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bar_hi = pci_pdev_read_cfg(pbdf, pci_bar_offset(bir + 1U), 4U);
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base |= ((uint64_t)bar_hi << 32U);
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}
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vdev->msix.mmio_hva = (uint64_t)hpa2hva(base);
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vdev->msix.mmio_gpa = vm0_hpa2gpa(base);
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/* Sizing the BAR */
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir), 4U, ~0U);
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size = pci_pdev_read_cfg(pbdf, pci_bar_offset(bir), 4U);
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vdev->msix.mmio_size = (size & ~(size - 1U));
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if ((bar_lo & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64) {
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir + 1U), 4U, ~0U);
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size = (uint64_t)pci_pdev_read_cfg(pbdf, pci_bar_offset(bir + 1U), 4U);
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vdev->msix.mmio_size |= (size << 32U);
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}
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/* Restore the BAR */
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir), 4U, bar_lo);
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if ((bar_lo & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64) {
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir + 1U), 4U, bar_hi);
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}
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}
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static int vmsix_init(struct pci_vdev *vdev)
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{
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uint32_t msgctrl;
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uint32_t table_info, i;
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struct msix *msix = &vdev->msix;
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msgctrl = pci_pdev_read_cfg(vdev->pdev.bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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/* Read Table Offset and Table BIR */
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table_info = pci_pdev_read_cfg(vdev->pdev.bdf, msix->capoff + PCIR_MSIX_TABLE, 4U);
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msix->table_bar = table_info & PCIM_MSIX_BIR_MASK;
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msix->table_offset = table_info & ~PCIM_MSIX_BIR_MASK;
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msix->table_count = (msgctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1U;
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/* Mask all table entries */
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for (i = 0U; i < msix->table_count; i++) {
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msix->tables[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
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}
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decode_msix_table_bar(vdev);
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/*
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* MSI-X table structures is in a 4 KB aligned range,
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* while it's possible that the MSI-X PBA co-reside within this
|
||||||
|
* naturally aligned 4 KB address range
|
||||||
|
*/
|
||||||
|
if (msix->mmio_gpa != 0U) {
|
||||||
|
(void)register_mmio_emulation_handler(vdev->vpci->vm, vmsix_table_mmio_access_handler,
|
||||||
|
msix->mmio_gpa, msix->mmio_gpa + msix->mmio_size, vdev);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int vmsix_deinit(struct pci_vdev *vdev)
|
||||||
|
{
|
||||||
|
if (vdev->msix.mmio_gpa != 0UL) {
|
||||||
|
unregister_mmio_emulation_handler(vdev->vpci->vm, vdev->msix.mmio_gpa,
|
||||||
|
vdev->msix.mmio_gpa + vdev->msix.mmio_size);
|
||||||
|
vdev->msix.mmio_gpa = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (vdev->msix.table_count != 0U) {
|
||||||
|
ptdev_remove_msix_remapping(vdev->vpci->vm, vdev->vbdf.value, vdev->msix.table_count);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct pci_vdev_ops pci_ops_vdev_msix = {
|
||||||
|
.init = vmsix_init,
|
||||||
|
.deinit = vmsix_deinit,
|
||||||
|
.cfgwrite = vmsix_cfgwrite,
|
||||||
|
.cfgread = vmsix_cfgread,
|
||||||
|
};
|
||||||
@ -75,6 +75,7 @@ pci_vdev_write_cfg_u32(struct pci_vdev *vdev, uint32_t offset, uint32_t val)
|
|||||||
|
|
||||||
extern struct vpci_ops partition_mode_vpci_ops;
|
extern struct vpci_ops partition_mode_vpci_ops;
|
||||||
extern struct pci_vdev_ops pci_ops_vdev_msi;
|
extern struct pci_vdev_ops pci_ops_vdev_msi;
|
||||||
|
extern struct pci_vdev_ops pci_ops_vdev_msix;
|
||||||
|
|
||||||
uint32_t pci_vdev_read_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes);
|
uint32_t pci_vdev_read_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes);
|
||||||
void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
|
void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
|
||||||
|
|||||||
@ -51,6 +51,12 @@ struct pci_bar {
|
|||||||
enum pci_bar_type type;
|
enum pci_bar_type type;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
struct msix_table_entry {
|
||||||
|
uint64_t addr;
|
||||||
|
uint32_t data;
|
||||||
|
uint32_t vector_control;
|
||||||
|
};
|
||||||
|
|
||||||
struct pci_pdev {
|
struct pci_pdev {
|
||||||
/* The bar info of the physical PCI device. */
|
/* The bar info of the physical PCI device. */
|
||||||
struct pci_bar bar[PCI_BAR_COUNT];
|
struct pci_bar bar[PCI_BAR_COUNT];
|
||||||
@ -65,6 +71,19 @@ struct msi {
|
|||||||
uint32_t caplen;
|
uint32_t caplen;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* MSI-X capability structure */
|
||||||
|
struct msix {
|
||||||
|
struct msix_table_entry tables[CONFIG_MAX_MSIX_TABLE_NUM];
|
||||||
|
uint64_t mmio_gpa;
|
||||||
|
uint64_t mmio_hva;
|
||||||
|
uint64_t mmio_size;
|
||||||
|
uint32_t capoff;
|
||||||
|
uint32_t caplen;
|
||||||
|
uint32_t table_bar;
|
||||||
|
uint32_t table_offset;
|
||||||
|
uint32_t table_count;
|
||||||
|
};
|
||||||
|
|
||||||
struct pci_vdev {
|
struct pci_vdev {
|
||||||
struct pci_vdev_ops *ops;
|
struct pci_vdev_ops *ops;
|
||||||
struct vpci *vpci;
|
struct vpci *vpci;
|
||||||
@ -80,6 +99,7 @@ struct pci_vdev {
|
|||||||
|
|
||||||
#ifndef CONFIG_PARTITION_MODE
|
#ifndef CONFIG_PARTITION_MODE
|
||||||
struct msi msi;
|
struct msi msi;
|
||||||
|
struct msix msix;
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user