mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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hv: implement msi.c to handle MSI remapping for vm0
Emulate MSI Capability structure for vm0 in sharing mode: - it intercepts the IO requests for MSI Capability structure, emulates the Message Control word, and bypasses all other I/O requests to the physical device. - criteria to trigger MSI remapping: MSI Enable bit is being changed, Message Data/Addr is being changed when MSI Enable is set. Tracked-On: #1568 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Zide Chen
lijinxia
parent
6af47f249c
commit
dcebdb8e98
@ -178,9 +178,13 @@ endif
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C_SRCS += dm/vpic.c
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C_SRCS += dm/vioapic.c
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ifeq ($(CONFIG_PARTITION_MODE),y)
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C_SRCS += $(wildcard dm/vpci/*.c)
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C_SRCS += $(wildcard partition/*.c)
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C_SRCS += dm/hw/pci.c
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C_SRCS += dm/vpci/core.c
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C_SRCS += dm/vpci/vpci.c
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C_SRCS += dm/vpci/partition_mode.c
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C_SRCS += dm/vpci/hostbridge.c
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C_SRCS += dm/vpci/pci_pt.c
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C_SRCS += dm/vrtc.c
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endif
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@ -99,6 +99,24 @@ void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint
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spinlock_release(&pci_device_lock);
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}
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/* enable: 1: enable INTx; 0: Disable INTx */
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void enable_disable_pci_intx(union pci_bdf bdf, bool enable)
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{
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uint32_t cmd, new_cmd;
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/* Set or clear the INTXDIS bit in COMMAND register */
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cmd = pci_pdev_read_cfg(bdf, PCIR_COMMAND, 2U);
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if (enable) {
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new_cmd = cmd & ~PCIM_CMD_INTxDIS;
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} else {
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new_cmd = cmd | PCIM_CMD_INTxDIS;
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}
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if ((cmd ^ new_cmd) != 0U) {
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pci_pdev_write_cfg(bdf, PCIR_COMMAND, 0x2U, new_cmd);
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}
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}
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#define BUS_SCAN_SKIP 0U
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#define BUS_SCAN_PENDING 1U
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#define BUS_SCAN_COMPLETE 2U
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229
hypervisor/dm/vpci/msi.c
Normal file
229
hypervisor/dm/vpci/msi.c
Normal file
@ -0,0 +1,229 @@
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/*
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <hypervisor.h>
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#include "pci_priv.h"
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static inline bool msicap_access(struct pci_vdev *vdev, uint32_t offset)
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{
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if (vdev->msi.capoff == 0U) {
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return 0;
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}
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return in_range(offset, vdev->msi.capoff, vdev->msi.caplen);
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}
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static int vmsi_remap(struct pci_vdev *vdev, bool enable)
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{
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struct ptdev_msi_info info;
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union pci_bdf pbdf = vdev->pdev.bdf;
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struct vm *vm = vdev->vpci->vm;
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uint32_t capoff = vdev->msi.capoff;
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uint32_t msgctrl, msgdata;
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uint32_t addrlo, addrhi;
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int ret;
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/* Disable MSI during configuration */
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msgctrl = pci_vdev_read_cfg(vdev, capoff + PCIR_MSI_CTRL, 2U);
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if ((msgctrl & PCIM_MSICTRL_MSI_ENABLE) == PCIM_MSICTRL_MSI_ENABLE) {
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_CTRL, 2U, msgctrl & ~PCIM_MSICTRL_MSI_ENABLE);
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}
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/* Read the MSI capability structure from virtual device */
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addrlo = pci_vdev_read_cfg_u32(vdev, capoff + PCIR_MSI_ADDR);
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if (msgctrl & PCIM_MSICTRL_64BIT) {
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msgdata = pci_vdev_read_cfg_u16(vdev, capoff + PCIR_MSI_DATA_64BIT);
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addrhi = pci_vdev_read_cfg_u32(vdev, capoff + PCIR_MSI_ADDR_HIGH);
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} else {
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msgdata = pci_vdev_read_cfg_u16(vdev, capoff + PCIR_MSI_DATA);
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addrhi = 0U;
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}
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info.is_msix = 0;
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info.vmsi_addr = (uint64_t)addrlo | ((uint64_t)addrhi << 32U);
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/* MSI is being enabled or disabled */
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if (enable) {
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info.vmsi_data = msgdata;
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} else {
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info.vmsi_data = 0U;
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}
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ret = ptdev_msix_remap(vm, vdev->vbdf.value, 0U, &info);
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if (ret != 0) {
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return ret;
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}
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/* Update MSI Capability structure to physical device */
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_ADDR, 0x4U, (uint32_t)info.pmsi_addr);
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if (msgctrl & PCIM_MSICTRL_64BIT) {
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_ADDR_HIGH, 0x4U, (uint32_t)(info.pmsi_addr >> 32U));
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_DATA_64BIT, 0x2U, (uint16_t)info.pmsi_data);
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} else {
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_DATA, 0x2U, (uint16_t)info.pmsi_data);
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}
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/* If MSI Enable is being set, make sure INTxDIS bit is set */
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if (enable) {
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enable_disable_pci_intx(pbdf, false);
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_CTRL, 2U, msgctrl | PCIM_MSICTRL_MSI_ENABLE);
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}
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return ret;
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}
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static int vmsi_cfgread(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val)
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{
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/* For PIO access, we emulate Capability Structures only */
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if (msicap_access(vdev, offset)) {
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*val = pci_vdev_read_cfg(vdev, offset, bytes);
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return 0;
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}
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return -ENODEV;
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}
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static int vmsi_cfgwrite(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val)
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{
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bool message_changed = false;
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bool enable;
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uint32_t msgctrl;
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/* Writing MSI Capability Structure */
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if (msicap_access(vdev, offset)) {
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/* Save msgctrl for comparison */
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msgctrl = pci_vdev_read_cfg(vdev, vdev->msi.capoff + PCIR_MSI_CTRL, 2U);
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/* Either Message Data or message Addr is being changed */
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if (((offset - vdev->msi.capoff) >= PCIR_MSI_ADDR) && (val != pci_vdev_read_cfg(vdev, offset, bytes))) {
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message_changed = true;
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}
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/* Write to vdev */
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pci_vdev_write_cfg(vdev, offset, bytes, val);
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/* Do remap if MSI Enable bit is being changed */
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if (((offset - vdev->msi.capoff) == PCIR_MSI_CTRL) && ((msgctrl ^ val) & PCIM_MSICTRL_MSI_ENABLE)) {
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enable = ((val & PCIM_MSICTRL_MSI_ENABLE) != 0U);
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(void)vmsi_remap(vdev, enable);
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} else {
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if (message_changed && ((msgctrl & PCIM_MSICTRL_MSI_ENABLE) != 0U)) {
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(void)vmsi_remap(vdev, true);
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}
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}
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return 0;
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}
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return -ENODEV;
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}
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void populate_msi_struct(struct pci_vdev *vdev)
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{
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uint8_t ptr, cap;
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uint32_t msgctrl;
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uint32_t len, bytes, offset, val;
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union pci_bdf pbdf = vdev->pdev.bdf;
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/* Has new Capabilities list? */
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if ((pci_pdev_read_cfg(pbdf, PCIR_STATUS, 2U) & PCIM_STATUS_CAPPRESENT) == 0U) {
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return;
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}
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ptr = (uint8_t)pci_pdev_read_cfg(pbdf, PCIR_CAP_PTR, 1U);
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while ((ptr != 0U) && (ptr != 0xFFU)) {
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cap = (uint8_t)pci_pdev_read_cfg(pbdf, ptr + PCICAP_ID, 1U);
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/* Ignore all other Capability IDs for now */
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if ((cap == PCIY_MSI) || (cap == PCIY_MSIX)) {
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offset = ptr;
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if (cap == PCIY_MSI) {
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vdev->msi.capoff = offset;
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msgctrl = pci_pdev_read_cfg(pbdf, offset + PCIR_MSI_CTRL, 2U);
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/*
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* Ignore the 'mask' and 'pending' bits in the MSI capability
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* (msgctrl & PCIM_MSICTRL_VECTOR).
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* We'll let the guest manipulate them directly.
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*/
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len = (msgctrl & PCIM_MSICTRL_64BIT) ? 14U : 10U;
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vdev->msi.caplen = len;
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/* Assign MSI handler for configuration read and write */
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add_vdev_handler(vdev, &pci_ops_vdev_msi);
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} else {
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vdev->msix.capoff = offset;
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vdev->msix.caplen = MSIX_CAPLEN;
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len = vdev->msix.caplen;
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/* Assign MSI-X handler for configuration read and write */
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add_vdev_handler(vdev, &pci_ops_vdev_msix);
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}
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/* Copy MSI/MSI-X capability struct into virtual device */
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while (len > 0U) {
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bytes = (len >= 4U) ? 4U : len;
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val = pci_pdev_read_cfg(pbdf, offset, bytes);
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if ((cap == PCIY_MSI) && (offset == vdev->msi.capoff)) {
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/*
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* Don't support multiple vector for now,
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* Force Multiple Message Enable and Multiple Message
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* Capable to 0
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*/
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val &= ~((uint32_t)PCIM_MSICTRL_MMC_MASK << 16U);
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val &= ~((uint32_t)PCIM_MSICTRL_MME_MASK << 16U);
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}
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pci_vdev_write_cfg(vdev, offset, bytes, val);
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len -= bytes;
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offset += bytes;
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}
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}
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ptr = (uint8_t)pci_pdev_read_cfg(pbdf, ptr + PCICAP_NEXTPTR, 1U);
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}
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}
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static int vmsi_deinit(struct pci_vdev *vdev)
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{
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if (vdev->msi.capoff != 0U) {
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ptdev_remove_msix_remapping(vdev->vpci->vm, vdev->vbdf.value, 1);
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}
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return 0;
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}
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struct pci_vdev_ops pci_ops_vdev_msi = {
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.init = NULL,
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.deinit = vmsi_deinit,
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.cfgwrite = vmsi_cfgwrite,
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.cfgread = vmsi_cfgread,
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};
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@ -32,6 +32,11 @@
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#include <pci.h>
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static inline bool in_range(uint32_t value, uint32_t lower, uint32_t len)
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{
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return ((value >= lower) && (value < (lower + len)));
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}
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static inline uint8_t
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pci_vdev_read_cfg_u8(struct pci_vdev *vdev, uint32_t offset)
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{
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@ -69,8 +74,11 @@ pci_vdev_write_cfg_u32(struct pci_vdev *vdev, uint32_t offset, uint32_t val)
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}
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extern struct vpci_ops partition_mode_vpci_ops;
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extern struct pci_vdev_ops pci_ops_vdev_msi;
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uint32_t pci_vdev_read_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes);
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void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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void populate_msi_struct(struct pci_vdev *vdev);
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#endif /* PCI_PRIV_H_ */
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@ -161,6 +161,7 @@ static inline bool pci_bar_access(uint32_t offset)
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uint32_t pci_pdev_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes);
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void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
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void enable_disable_pci_intx(union pci_bdf bdf, bool enable);
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void pci_scan_bus(pci_enumeration_cb cb, void *data);
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@ -59,6 +59,12 @@ struct pci_pdev {
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union pci_bdf bdf;
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};
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/* MSI capability structure */
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struct msi {
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uint32_t capoff;
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uint32_t caplen;
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};
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struct pci_vdev {
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struct pci_vdev_ops *ops;
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struct vpci *vpci;
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@ -71,6 +77,10 @@ struct pci_vdev {
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/* The bar info of the virtual PCI device. */
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struct pci_bar bar[PCI_BAR_COUNT];
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#ifndef CONFIG_PARTITION_MODE
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struct msi msi;
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#endif
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};
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struct pci_addr_info {
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