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HV: emulate MSR_TEST_CTL

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If CPU has MSR_TEST_CTL, show an emulaued one to VCPU

Tracked-On: #4496
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Reviewed-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
yuhong.tao@intel.com 2020-03-17 21:48:41 +08:00 committed by wenlingz
parent dd3fa8ed75
commit 7c80acee95
2 changed files with 28 additions and 1 deletions
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27
hypervisor/arch/x86/guest/vmsr.c
View File

@ -58,6 +58,8 @@ static const uint32_t emulated_guest_msrs[NUM_GUEST_MSRS] = {
MSR_IA32_SGXLEPUBKEYHASH3,
/* Read only */
MSR_IA32_SGX_SVN_STATUS,
MSR_TEST_CTL,
};
#define NUM_MTRR_MSRS 13U
@ -498,6 +500,18 @@ int32_t rdmsr_vmexit_handler(struct acrn_vcpu *vcpu)
}
break;
}
case MSR_TEST_CTL:
{
/* If has MSR_TEST_CTL, give emulated value
* If don't have MSR_TEST_CTL, trigger #GP
*/
if (has_core_cap(1U << 5U)) {
v = vcpu_get_guest_msr(vcpu, MSR_TEST_CTL);
} else {
vcpu_inject_gp(vcpu, 0U);
}
break;
}
default:
{
if (is_x2apic_msr(msr)) {
@ -802,6 +816,19 @@ int32_t wrmsr_vmexit_handler(struct acrn_vcpu *vcpu)
set_guest_ia32_misc_enalbe(vcpu, v);
break;
}
case MSR_TEST_CTL:
{
/* If VM has MSR_TEST_CTL, ignore write operation
* If don't have MSR_TEST_CTL, trigger #GP
*/
if (has_core_cap(1U << 5U)) {
vcpu_set_guest_msr(vcpu, MSR_TEST_CTL, v);
pr_warn("Ignore writting 0x%llx to MSR_TEST_CTL from VM%d", v, vcpu->vm->vm_id);
} else {
vcpu_inject_gp(vcpu, 0U);
}
break;
}
default:
{
if (is_x2apic_msr(msr)) {

2
hypervisor/include/arch/x86/guest/vcpu.h
View File

@ -159,7 +159,7 @@ enum reset_mode;
#define SECURE_WORLD 1
#define NUM_WORLD_MSRS 2U
#define NUM_COMMON_MSRS 15U
#define NUM_COMMON_MSRS 16U
#define NUM_GUEST_MSRS (NUM_WORLD_MSRS + NUM_COMMON_MSRS)
#define EOI_EXIT_BITMAP_SIZE 256U