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HV: enable #AC for Splitlock Access

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If CPU support rise #AC for Splitlock Access, then enable this
feature at each CPU.

Tracked-On: #4496
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Reviewed-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
yuhong.tao@intel.com 2020-03-25 22:11:11 +08:00 committed by wenlingz
parent ea1bce0cbf
commit dd3fa8ed75
2 changed files with 15 additions and 0 deletions
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14
hypervisor/arch/x86/cpu.c
View File

@ -98,6 +98,17 @@ uint64_t get_active_pcpu_bitmap(void)
return pcpu_active_bitmap;
}
static void enable_ac_for_splitlock(void)
{
uint64_t test_ctl;
if (has_core_cap(1U << 5U)) {
test_ctl = msr_read(MSR_TEST_CTL);
test_ctl |= (1U << 29U);
msr_write(MSR_TEST_CTL, test_ctl);
}
}
void init_pcpu_pre(bool is_bsp)
{
uint16_t pcpu_id;
@ -166,6 +177,7 @@ void init_pcpu_pre(bool is_bsp)
*/
pci_switch_to_mmio_cfg_ops();
} else {
/* Switch this CPU to use the same page tables set-up by the
* primary/boot CPU
*/
@ -192,6 +204,8 @@ void init_pcpu_post(uint16_t pcpu_id)
#endif
load_gdtr_and_tr();
enable_ac_for_splitlock();
init_pcpu_xsave();
if (pcpu_id == BSP_CPU_ID) {

1
hypervisor/include/arch/x86/msr.h
View File

@ -18,6 +18,7 @@
#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010U
#define MSR_IA32_PLATFORM_ID 0x00000017U
#define MSR_IA32_APIC_BASE 0x0000001BU
#define MSR_TEST_CTL 0x00000033U
#define MSR_IA32_FEATURE_CONTROL 0x0000003AU
#define MSR_IA32_TSC_ADJUST 0x0000003BU
/* Speculation Control */