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acrn-config: add MAX_CACHE_CLOS_NUM_ENTRIES/MAX_MBA_CLOS_NUM_ENTRIES macros

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1.Add macro MAX_CACHE_CLOS_NUM_ENTRIES for CAT, and MAX_MBA_CLOS_NUM_ENTRIES for MBA.

 MAX_MBA_CLOS_NUM_ENTRIES:
  Max number of Cache Mask entries corresponding to each CLOS.
  This can vary if CDP is enabled vs disabled, as each CLOS entry will have corresponding
  cache mask values for Data and Code when CDP is enabled.

 MAX_CACHE_CLOS_NUM_ENTRIES:
  Max number of MBA delay entries corresponding to each CLOS.

2.Move VMx_VCPU_CLOS macro to misc_cfg.h head file.

Tracked-On: #5229
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This commit is contained in:
Wei Liu
2020-08-23 17:05:46 -07:00
committed by wenlingz
parent a425730f64
commit 7eb103478a
7 changed files with 60 additions and 38 deletions
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2
misc/vm_configs/xmls/config-xmls/ehl-crb-b/industry.xml
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@@ -117,10 +117,12 @@
<guest_flag>0</guest_flag>
</guest_flags>
<cpu_affinity desc="List of pCPU: the guest VM is allowed to create vCPU from all or a subset of this list.">
<pcpu_id>0</pcpu_id>
<pcpu_id>1</pcpu_id>
</cpu_affinity>
<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
<vcpu_clos>0</vcpu_clos>
<vcpu_clos>0</vcpu_clos>
</clos>
<epc_section configurable="0" desc="epc section">
<base desc="SGX EPC section base, must be page aligned">0</base>