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acrn-config: add MMCFG_BASE_INFO item in board config

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Parse MMCFG base address value and store it to board config xml
as DEFAULT_PCI_MMCFG_BASE macro.

Tracked-On: #4173
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This commit is contained in:
Wei Liu 2019-12-02 10:04:37 +08:00 committed by wenlingz
parent 0e273e996c
commit 80a7281f1e
7 changed files with 35 additions and 0 deletions
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5
misc/acrn-config/xmls/board-xmls/apl-mrb.xml
View File

@ -253,6 +253,11 @@
{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P16 */ {0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P16 */
</PX_INFO> </PX_INFO>
<MMCFG_BASE_INFO>
/* PCI mmcfg base of MCFG */
#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL
</MMCFG_BASE_INFO>
<CLOS_INFO> <CLOS_INFO>
clos supported by cache:L2 clos supported by cache:L2
clos max:4 clos max:4

5
misc/acrn-config/xmls/board-xmls/apl-up2-n3350.xml
View File

@ -227,6 +227,11 @@
{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P4 */ {0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P4 */
</PX_INFO> </PX_INFO>
<MMCFG_BASE_INFO>
/* PCI mmcfg base of MCFG */
#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL
</MMCFG_BASE_INFO>
<CLOS_INFO> <CLOS_INFO>
clos supported by cache:L2 clos supported by cache:L2
clos max:4 clos max:4

5
misc/acrn-config/xmls/board-xmls/apl-up2.xml
View File

@ -227,6 +227,11 @@
{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P4 */ {0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P4 */
</PX_INFO> </PX_INFO>
<MMCFG_BASE_INFO>
/* PCI mmcfg base of MCFG */
#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL
</MMCFG_BASE_INFO>
<CLOS_INFO> <CLOS_INFO>
clos supported by cache:L2 clos supported by cache:L2
clos max:4 clos max:4

5
misc/acrn-config/xmls/board-xmls/nuc6cayh.xml
View File

@ -183,6 +183,11 @@
{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P8 */ {0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P8 */
</PX_INFO> </PX_INFO>
<MMCFG_BASE_INFO>
/* PCI mmcfg base of MCFG */
#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL
</MMCFG_BASE_INFO>
<CLOS_INFO> <CLOS_INFO>
clos supported by cache:L2 clos supported by cache:L2
clos max:4 clos max:4

5
misc/acrn-config/xmls/board-xmls/nuc7i7dnb.xml
View File

@ -181,6 +181,11 @@
{0x190UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000400UL, 0x000400UL}, /* P15 */ {0x190UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000400UL, 0x000400UL}, /* P15 */
</PX_INFO> </PX_INFO>
<MMCFG_BASE_INFO>
/* PCI mmcfg base of MCFG */
#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL
</MMCFG_BASE_INFO>
<CLOS_INFO> <CLOS_INFO>
clos supported by cache:False clos supported by cache:False
clos max:0 clos max:0

5
misc/acrn-config/xmls/board-xmls/whl-ipc-i5.xml
View File

@ -173,6 +173,11 @@
{0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P5 */ {0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P5 */
</PX_INFO> </PX_INFO>
<MMCFG_BASE_INFO>
/* PCI mmcfg base of MCFG */
#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL
</MMCFG_BASE_INFO>
<CLOS_INFO> <CLOS_INFO>
clos supported by cache:False clos supported by cache:False
clos max:0 clos max:0

5
misc/acrn-config/xmls/board-xmls/whl-ipc-i7.xml
View File

@ -177,6 +177,11 @@
{0x514UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000D00UL, 0x000D00UL}, /* P9 */ {0x514UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000D00UL, 0x000D00UL}, /* P9 */
</PX_INFO> </PX_INFO>
<MMCFG_BASE_INFO>
/* PCI mmcfg base of MCFG */
#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL
</MMCFG_BASE_INFO>
<CLOS_INFO> <CLOS_INFO>
clos supported by cache:False clos supported by cache:False
clos max:0 clos max:0