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HV: treewide: fix violations of coding guideline C-TY-27 & C-TY-28

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The coding guideline rules C-TY-27 and C-TY-28, combined, requires that
assignment and arithmetic operations shall be applied only on operands of the
same kind. This patch either adds explicit type casts or adjust types of
variables to align the types of operands.

The only semantic change introduced by this patch is the promotion of the
second argument of set_vmcs_bit() and clear_vmcs_bit() to
uint64_t (formerly uint32_t). This avoids clear_vmcs_bit() to accidentally
clears the upper 32 bits of the requested VMCS field.

Other than that, this patch has no semantic change. Specifically this patch
is not meant to fix buggy narrowing operations, only to make these
operations explicit.

Tracked-On: #6776
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Junjie Mao
2021-10-29 16:02:10 +08:00
committed by wenlingz
parent 2c86795fa8
commit 83a938bae6
27 changed files with 51 additions and 50 deletions
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4
hypervisor/include/arch/x86/asm/guest/vmcs.h
View File

@@ -41,7 +41,7 @@ static inline uint64_t apic_access_offset(uint64_t qual)
return (qual & APIC_ACCESS_OFFSET);
}
static inline void clear_vmcs_bit(uint32_t vmcs_field, uint32_t bit)
static inline void clear_vmcs_bit(uint32_t vmcs_field, uint64_t bit)
{
uint64_t val64;
@@ -50,7 +50,7 @@ static inline void clear_vmcs_bit(uint32_t vmcs_field, uint32_t bit)
exec_vmwrite(vmcs_field, val64);
}
static inline void set_vmcs_bit(uint32_t vmcs_field, uint32_t bit)
static inline void set_vmcs_bit(uint32_t vmcs_field, uint64_t bit)
{
uint64_t val64;

2
hypervisor/include/arch/x86/asm/mmu.h
View File

@@ -183,7 +183,7 @@ void flush_vpid_global(void);
*/
void invept(const void *eptp);
uint32_t get_hv_ram_size(void);
uint64_t get_hv_ram_size(void);
/* get PDPT address from CR3 vaule in PAE mode */
static inline uint64_t get_pae_pdpt_addr(uint64_t cr3)

6
hypervisor/include/arch/x86/asm/msr.h
View File

@@ -596,9 +596,9 @@
/* 5 high-order bits in every field are reserved */
#define PAT_FIELD_RSV_BITS (0xF8UL)
/* MSR_TEST_CTL bits */
#define MSR_TEST_CTL_GP_UCLOCK (1U << 28U)
#define MSR_TEST_CTL_AC_SPLITLOCK (1U << 29U)
#define MSR_TEST_CTL_DISABLE_LOCK_ASSERTION (1U << 31U)
#define MSR_TEST_CTL_GP_UCLOCK (1UL << 28U)
#define MSR_TEST_CTL_AC_SPLITLOCK (1UL << 29U)
#define MSR_TEST_CTL_DISABLE_LOCK_ASSERTION (1UL << 31U)
#ifndef ASSEMBLER
static inline bool is_pat_mem_type_invalid(uint64_t x)