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HV:treewide:Fix type conversion in VMX, timer and MTTR module

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There are some integer type conversions in the VMX, timer
and MTTR module detected by static analysis tool.

Update related integer type in VMX, timer and MTTR
module.
Add related constant value with 'U/UL' suffix.

V1-->V2:
        Resolve few rebase conflicts.
V2-->V3:
        Add 'h' for uint16_t argument in log function;
	Update the type of temp variable 'type' as uint8_t
	in MTTR module to reduce type conversion.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Xiangyang Wu
2018-07-18 10:27:04 +08:00
committed by lijinxia
parent f7efd0fee5
commit 84d320d49c
8 changed files with 207 additions and 206 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
hypervisor/include/arch/x86/cpu.h
View File

@@ -53,21 +53,21 @@
#define CPU_STACK_ALIGN 16UL
/* CR0 register definitions */
#define CR0_PG (1U<<31) /* paging enable */
#define CR0_CD (1U<<30) /* cache disable */
#define CR0_NW (1U<<29) /* not write through */
#define CR0_AM (1U<<18) /* alignment mask */
#define CR0_WP (1U<<16) /* write protect */
#define CR0_NE (1U<<5) /* numeric error */
#define CR0_ET (1U<<4) /* extension type */
#define CR0_TS (1U<<3) /* task switched */
#define CR0_EM (1U<<2) /* emulation */
#define CR0_MP (1U<<1) /* monitor coprocessor */
#define CR0_PE (1U<<0) /* protected mode enabled */
#define CR0_PG (1UL<<31U) /* paging enable */
#define CR0_CD (1UL<<30U) /* cache disable */
#define CR0_NW (1UL<<29U) /* not write through */
#define CR0_AM (1UL<<18U) /* alignment mask */
#define CR0_WP (1UL<<16U) /* write protect */
#define CR0_NE (1UL<<5U) /* numeric error */
#define CR0_ET (1UL<<4U) /* extension type */
#define CR0_TS (1UL<<3U) /* task switched */
#define CR0_EM (1UL<<2U) /* emulation */
#define CR0_MP (1UL<<1U) /* monitor coprocessor */
#define CR0_PE (1UL<<0U) /* protected mode enabled */
/* CR3 register definitions */
#define CR3_PWT (1U<<3) /* page-level write through */
#define CR3_PCD (1U<<4) /* page-level cache disable */
#define CR3_PWT (1UL<<3U) /* page-level write through */
#define CR3_PCD (1UL<<4U) /* page-level cache disable */
/* CR4 register definitions */
#define CR4_VME (1UL<<0) /* virtual 8086 mode extensions */

16
hypervisor/include/arch/x86/gdt.h
View File

@@ -27,9 +27,9 @@
* bytes.
* Task State Segment (TSS) selectors are 16 bytes on x86-64 instead of 8 bytes.
*/
#define X64_SEG_DESC_SIZE (0x8) /* In long mode SEG Descriptors are 8 bytes */
#define X64_LDT_DESC_SIZE (0x10)/* In long mode LDT Descriptors are 16 bytes */
#define X64_TSS_DESC_SIZE (0x10)/* In long mode TSS Descriptors are 16 bytes */
#define X64_SEG_DESC_SIZE (0x8U) /* In long mode SEG Descriptors are 8 bytes */
#define X64_LDT_DESC_SIZE (0x10U)/* In long mode LDT Descriptors are 16 bytes */
#define X64_TSS_DESC_SIZE (0x10U)/* In long mode TSS Descriptors are 16 bytes */
/*****************************************************************************
*
@@ -41,13 +41,13 @@
*
*****************************************************************************/
/* Number of global 8 byte segments descriptor(s) */
#define HOST_GDT_RING0_SEG_SELECTORS (0x3) /* rsvd, code, data */
#define HOST_GDT_RING0_SEG_SELECTORS (0x3U) /* rsvd, code, data */
/* Offsets of global 8 byte segment descriptors */
#define HOST_GDT_RING0_RSVD_SEL (0x0000)
#define HOST_GDT_RING0_CODE_SEL (0x0008)
#define HOST_GDT_RING0_DATA_SEL (0x0010)
#define HOST_GDT_RING0_RSVD_SEL (0x0000U)
#define HOST_GDT_RING0_CODE_SEL (0x0008U)
#define HOST_GDT_RING0_DATA_SEL (0x0010U)
/* Number of global 16 byte LDT descriptor(s) */
#define HOST_GDT_RING0_TSS_SELECTORS (0x1)
#define HOST_GDT_RING0_TSS_SELECTORS (0x1U)
/* One for each CPU in the hypervisor. */
/*****************************************************************************

58
hypervisor/include/arch/x86/msr.h
View File

@@ -492,10 +492,10 @@
#define MSR_LNC_BIOS_CACHE_AS_RAM 0x000002E0U /* Configure CAR */
/* EFER bits */
#define MSR_IA32_EFER_SCE_BIT (1U<<0)
#define MSR_IA32_EFER_LME_BIT (1U<<8) /* IA32e mode enable */
#define MSR_IA32_EFER_LMA_BIT (1U<<10) /* IA32e mode active */
#define MSR_IA32_EFER_NXE_BIT (1U<<11)
#define MSR_IA32_EFER_SCE_BIT (1UL<<0U)
#define MSR_IA32_EFER_LME_BIT (1UL<<8U) /* IA32e mode enable */
#define MSR_IA32_EFER_LMA_BIT (1UL<<10U) /* IA32e mode active */
#define MSR_IA32_EFER_NXE_BIT (1UL<<11U)
/* FEATURE CONTROL bits */
#define MSR_IA32_FEATURE_CONTROL_LOCK (1U<<0)
@@ -503,12 +503,12 @@
#define MSR_IA32_FEATURE_CONTROL_VMX_NO_SMX (1U<<2)
/* PAT memory type definitions */
#define PAT_MEM_TYPE_UC 0x00U /* uncached */
#define PAT_MEM_TYPE_WC 0x01U /* write combining */
#define PAT_MEM_TYPE_WT 0x04U /* write through */
#define PAT_MEM_TYPE_WP 0x05U /* write protected */
#define PAT_MEM_TYPE_WB 0x06U /* writeback */
#define PAT_MEM_TYPE_UCM 0x07U /* uncached minus */
#define PAT_MEM_TYPE_UC 0x00UL /* uncached */
#define PAT_MEM_TYPE_WC 0x01UL /* write combining */
#define PAT_MEM_TYPE_WT 0x04UL /* write through */
#define PAT_MEM_TYPE_WP 0x05UL /* write protected */
#define PAT_MEM_TYPE_WB 0x06UL /* writeback */
#define PAT_MEM_TYPE_UCM 0x07UL /* uncached minus */
#define PAT_MEM_TYPE_INVALID(x) (((x) != PAT_MEM_TYPE_UC) && \
((x) != PAT_MEM_TYPE_WC) && \
((x) != PAT_MEM_TYPE_WT) && \
@@ -520,29 +520,29 @@
#define PAT_FIELD_RSV_BITS (0xF8U)
#define PAT_POWER_ON_VALUE (PAT_MEM_TYPE_WB + \
((uint64_t)PAT_MEM_TYPE_WT << 8) + \
((uint64_t)PAT_MEM_TYPE_UCM << 16) + \
((uint64_t)PAT_MEM_TYPE_UC << 24) + \
((uint64_t)PAT_MEM_TYPE_WB << 32) + \
((uint64_t)PAT_MEM_TYPE_WT << 40) + \
((uint64_t)PAT_MEM_TYPE_UCM << 48) + \
((uint64_t)PAT_MEM_TYPE_UC << 56))
(PAT_MEM_TYPE_WT << 8U) + \
(PAT_MEM_TYPE_UCM << 16U) + \
(PAT_MEM_TYPE_UC << 24U) + \
(PAT_MEM_TYPE_WB << 32U) + \
(PAT_MEM_TYPE_WT << 40U) + \
(PAT_MEM_TYPE_UCM << 48U) + \
(PAT_MEM_TYPE_UC << 56U))
#define PAT_ALL_UC_VALUE (PAT_MEM_TYPE_UC + \
((uint64_t)PAT_MEM_TYPE_UC << 8) + \
((uint64_t)PAT_MEM_TYPE_UC << 16) + \
((uint64_t)PAT_MEM_TYPE_UC << 24) + \
((uint64_t)PAT_MEM_TYPE_UC << 32) + \
((uint64_t)PAT_MEM_TYPE_UC << 40) + \
((uint64_t)PAT_MEM_TYPE_UC << 48) + \
((uint64_t)PAT_MEM_TYPE_UC << 56))
(PAT_MEM_TYPE_UC << 8U) + \
(PAT_MEM_TYPE_UC << 16U) + \
(PAT_MEM_TYPE_UC << 24U) + \
(PAT_MEM_TYPE_UC << 32U) + \
(PAT_MEM_TYPE_UC << 40U) + \
(PAT_MEM_TYPE_UC << 48U) + \
(PAT_MEM_TYPE_UC << 56U))
/* MTRR memory type definitions */
#define MTRR_MEM_TYPE_UC 0x00U /* uncached */
#define MTRR_MEM_TYPE_WC 0x01U /* write combining */
#define MTRR_MEM_TYPE_WT 0x04U /* write through */
#define MTRR_MEM_TYPE_WP 0x05U /* write protected */
#define MTRR_MEM_TYPE_WB 0x06U /* writeback */
#define MTRR_MEM_TYPE_UC 0x00UL /* uncached */
#define MTRR_MEM_TYPE_WC 0x01UL /* write combining */
#define MTRR_MEM_TYPE_WT 0x04UL /* write through */
#define MTRR_MEM_TYPE_WP 0x05UL /* write protected */
#define MTRR_MEM_TYPE_WB 0x06UL /* writeback */
/* misc. MTRR flag definitions */
#define MTRR_ENABLE 0x800U /* MTRR enable */

4
hypervisor/include/arch/x86/mtrr.h
View File

@@ -6,8 +6,8 @@
#ifndef MTRR_H
#define MTRR_H
#define FIXED_RANGE_MTRR_NUM 11
#define MTRR_SUB_RANGE_NUM 8
#define FIXED_RANGE_MTRR_NUM 11U
#define MTRR_SUB_RANGE_NUM 8U
union mtrr_cap_reg {
uint64_t value;