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https://github.com/projectacrn/acrn-hypervisor.git
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hv: mmu: replace modify_mem with mmu_modify
Signed-off-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
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0a33c0deee
commit
f7efd0fee5
@ -35,7 +35,6 @@ static void *mmu_pml4_addr;
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enum mem_map_request_type {
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PAGING_REQUEST_TYPE_MAP = 0, /* Creates a new mapping. */
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PAGING_REQUEST_TYPE_UNMAP = 1, /* Removes a pre-existing entry */
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PAGING_REQUEST_TYPE_MODIFY = 2,
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/* Modifies a pre-existing entries attributes. */
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PAGING_REQUEST_TYPE_UNKNOWN,
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};
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@ -366,25 +365,6 @@ static uint32_t map_mem_region(void *vaddr, void *paddr,
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}
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break;
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}
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case PAGING_REQUEST_TYPE_MODIFY:
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{
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/* Allow mapping or modification as requested. */
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table_entry = ((table_type == PTT_EPT)
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? attr : (attr | IA32E_COMM_P_BIT));
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table_entry |= (uint64_t) paddr;
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/* Write the table entry to map this memory */
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mem_write64(table_base + table_offset, table_entry);
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/* Modify, need to invalidate TLB and
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* page-structure cache
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*/
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if (table_type == PTT_HOST) {
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mmu_need_invtlb = true;
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}
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break;
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}
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default:
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ASSERT(false, "Bad memory map request type");
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return 0;
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@ -581,9 +561,6 @@ void init_paging(void)
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struct e820_entry *entry;
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uint64_t hv_hpa;
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uint32_t i;
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int attr_wb = (MMU_MEM_ATTR_BIT_READ_WRITE |
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MMU_MEM_ATTR_BIT_USER_ACCESSIBLE |
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MMU_MEM_ATTR_TYPE_CACHED_WB);
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int attr_uc = (MMU_MEM_ATTR_BIT_READ_WRITE |
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MMU_MEM_ATTR_BIT_USER_ACCESSIBLE |
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MMU_MEM_ATTR_TYPE_UNCACHED);
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@ -610,9 +587,10 @@ void init_paging(void)
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for (i = 0U; i < e820_entries; i++) {
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entry = &e820[i];
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if (entry->type == E820_TYPE_RAM) {
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modify_mem(&map_params, (void *)entry->baseaddr,
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(void *)entry->baseaddr,
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entry->length, attr_wb);
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mmu_modify((uint64_t *)mmu_pml4_addr,
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entry->baseaddr, entry->length,
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PAGE_CACHE_WB, PAGE_CACHE_MASK,
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PTT_HOST);
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}
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}
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@ -620,10 +598,8 @@ void init_paging(void)
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* to supervisor-mode for hypervisor owned memroy.
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*/
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hv_hpa = get_hv_image_base();
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modify_mem(&map_params, (void *)hv_hpa, (void *)hv_hpa,
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CONFIG_RAM_SIZE, attr_wb & (~MMU_MEM_ATTR_BIT_USER_ACCESSIBLE));
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pr_dbg("Enabling MMU ");
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mmu_modify((uint64_t *)mmu_pml4_addr, hv_hpa, CONFIG_RAM_SIZE,
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PAGE_CACHE_WB, PAGE_CACHE_MASK | PAGE_USER, PTT_HOST);
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/* Enable paging */
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enable_paging(HVA2HPA(mmu_pml4_addr));
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@ -1088,22 +1064,3 @@ int unmap_mem(struct map_params *map_params, void *paddr, void *vaddr,
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}
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return ret;
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}
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int modify_mem(struct map_params *map_params, void *paddr, void *vaddr,
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uint64_t size, uint32_t flags)
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{
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int ret = 0;
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/* used for MMU and EPT*/
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ret = modify_paging(map_params, paddr, vaddr, size, flags,
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PAGING_REQUEST_TYPE_MODIFY, true);
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if (ret < 0) {
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return ret;
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}
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/* only for EPT */
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if (map_params->page_table_type == PTT_EPT) {
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ret = modify_paging(map_params, vaddr, paddr, size, flags,
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PAGING_REQUEST_TYPE_MODIFY, false);
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}
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return ret;
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}
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@ -325,8 +325,6 @@ int map_mem(struct map_params *map_params, void *paddr, void *vaddr,
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uint64_t size, uint32_t flags);
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int unmap_mem(struct map_params *map_params, void *paddr, void *vaddr,
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uint64_t size, uint32_t flags);
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int modify_mem(struct map_params *map_params, void *paddr, void *vaddr,
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uint64_t size, uint32_t flags);
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int mmu_modify(uint64_t *pml4_page,
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uint64_t vaddr_base, uint64_t size,
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uint64_t prot_set, uint64_t prot_clr,
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