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https://github.com/projectacrn/acrn-hypervisor.git
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hv: nested: define software layout for VMCS12 and helper functions
Software layout of VMCS12 data is a contract between L1 guest and L0 hypervisor to run a L2 guest. ACRN hypervisor caches the VMCS12 which is passed down from L1 hypervisor by the VMPTRLD instructin. At the time of VMCLEAR, ACRN syncs the cached VMCS12 back to L1 guest memory. Tracked-On: #5923 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@Intel.com>
This commit is contained in:
Zide Chen
wenlingz
parent
f5744174b5
commit
863e58e539
@ -228,9 +228,157 @@ int32_t read_vmx_msr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t *val)
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return err;
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}
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/* make it 1 to be able to build. correctly initialize it in next patch */
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#define MAX_SHADOW_VMCS_FIELDS 1
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/*
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* VMCS fields included in the dual-purpose VMCS: as shadow for L1 and
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* as hardware VMCS for nested guest (L2).
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*
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* TODO: This list is for TGL and CFL machines and the fields
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* for advacned APICv features such as Posted Interrupt and Virtual
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* Interrupt Delivery are not included, as these are not available
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* on those platforms.
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*
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* Certain fields, e.g. VMX_TSC_MULTIPLIER_FULL is available only if
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* "use TSC scaling” is supported. Thus a static array may not work
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* for all platforms.
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*/
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static const uint32_t vmcs_shadowing_fields[MAX_SHADOW_VMCS_FIELDS] = {
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};
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/* to be shared by all vCPUs for all nested guests */
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static uint64_t vmcs_shadowing_bitmap[PAGE_SIZE / sizeof(uint64_t)] __aligned(PAGE_SIZE);
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/*
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* This is an array of offsets into a structure of type "struct acrn_vmcs12"
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* 16 offsets for a total of 16 GROUPs. 4 "field widths" by 4 "field types".
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* "Field type" is either Control, Read-Only Data, Guest State or Host State.
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* Refer to the definition of "struct acrn_vmcs12" on how the fields are
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* grouped together for these offsets to work in tandem.
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* Refer to Intel SDM Appendix B Field Encoding in VMCS for info on how
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* fields are grouped and indexed within a group.
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*/
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static const uint16_t vmcs12_group_offset_table[16] = {
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offsetof(struct acrn_vmcs12, vpid), /* 16-bit Control Fields */
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offsetof(struct acrn_vmcs12, padding), /* 16-bit Read-Only Fields */
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offsetof(struct acrn_vmcs12, guest_es), /* 16-bit Guest-State Fields */
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offsetof(struct acrn_vmcs12, host_es), /* 16-bit Host-State Fields */
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offsetof(struct acrn_vmcs12, io_bitmap_a), /* 64-bit Control Fields */
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offsetof(struct acrn_vmcs12, guest_phys_addr), /* 64-bit Read-Only Data Fields */
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offsetof(struct acrn_vmcs12, vmcs_link_ptr), /* 64-bit Guest-State Fields */
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offsetof(struct acrn_vmcs12, host_ia32_pat), /* 64-bit Host-State Fields */
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offsetof(struct acrn_vmcs12, pin_based_exec_ctrl), /* 32-bit Control Fields */
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offsetof(struct acrn_vmcs12, vm_instr_error), /* 32-bit Read-Only Data Fields */
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offsetof(struct acrn_vmcs12, guest_es_limit), /* 32-bit Guest-State Fields */
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offsetof(struct acrn_vmcs12, host_ia32_sysenter_cs), /* 32-bit Host-State Fields */
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offsetof(struct acrn_vmcs12, cr0_guest_host_mask), /* Natural-width Control Fields */
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offsetof(struct acrn_vmcs12, exit_qual), /* Natural-width Read-Only Data Fields */
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offsetof(struct acrn_vmcs12, guest_cr0), /* Natural-width Guest-State Fields */
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offsetof(struct acrn_vmcs12, host_cr0), /* Natural-width Host-State Fields */
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};
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/*
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* field_idx is the index of the field within the group.
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*
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* Access-type is 0 for all widths except for 64-bit
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* For 64-bit if Access-type is 1, offset is moved to
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* high 4 bytes of the field.
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*/
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#define OFFSET_INTO_VMCS12(group_idx, field_idx, width_in_bytes, access_type) \
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(vmcs12_group_offset_table[group_idx] + \
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field_idx * width_in_bytes + \
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access_type * sizeof(uint32_t))
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/* Given a vmcs field, this API returns the offset into "struct acrn_vmcs12" */
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static uint16_t vmcs_field_to_vmcs12_offset(uint32_t vmcs_field)
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{
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/*
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* Refer to Appendix B Field Encoding in VMCS in SDM
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* A value of group index 0001b is not valid because there are no 16-bit
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* Read-Only fields.
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*
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* TODO: check invalid VMCS field
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*/
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uint16_t group_idx = (VMX_VMCS_FIELD_WIDTH(vmcs_field) << 2U) | VMX_VMCS_FIELD_TYPE(vmcs_field);
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uint8_t field_width = VMX_VMCS_FIELD_WIDTH(vmcs_field);
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uint8_t width_in_bytes;
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if (field_width == VMX_VMCS_FIELD_WIDTH_16) {
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width_in_bytes = 2U;
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} else if (field_width == VMX_VMCS_FIELD_WIDTH_32) {
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width_in_bytes = 4U;
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} else {
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/*
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* Natural-width or 64-bit
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*/
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width_in_bytes = 8U;
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}
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return OFFSET_INTO_VMCS12(group_idx,
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VMX_VMCS_FIELD_INDEX(vmcs_field), width_in_bytes, /* field index within the group */
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VMX_VMCS_FIELD_ACCESS_HIGH(vmcs_field));
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}
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/*
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* Given a vmcs field and the pointer to the vmcs12, this API returns the
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* corresponding value from the VMCS
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*/
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static uint64_t vmcs12_read_field(uint64_t vmcs_hva, uint32_t field)
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{
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uint64_t *ptr = (uint64_t *)(vmcs_hva + vmcs_field_to_vmcs12_offset(field));
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uint64_t val64 = 0UL;
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switch (VMX_VMCS_FIELD_WIDTH(field)) {
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case VMX_VMCS_FIELD_WIDTH_16:
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val64 = *(uint16_t *)ptr;
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break;
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case VMX_VMCS_FIELD_WIDTH_32:
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val64 = *(uint32_t *)ptr;
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break;
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case VMX_VMCS_FIELD_WIDTH_64:
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if (!!VMX_VMCS_FIELD_ACCESS_HIGH(field)) {
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val64 = *(uint32_t *)ptr;
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} else {
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val64 = *ptr;
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}
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break;
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case VMX_VMCS_FIELD_WIDTH_NATURAL:
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default:
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val64 = *ptr;
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break;
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}
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return val64;
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}
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/*
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* Write the given VMCS field to the given vmcs12 data structure.
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*/
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static void vmcs12_write_field(uint64_t vmcs_hva, uint32_t field, uint64_t val64)
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{
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uint64_t *ptr = (uint64_t *)(vmcs_hva + vmcs_field_to_vmcs12_offset(field));
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switch (VMX_VMCS_FIELD_WIDTH(field)) {
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case VMX_VMCS_FIELD_WIDTH_16:
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*(uint16_t *)ptr = (uint16_t)val64;
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break;
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case VMX_VMCS_FIELD_WIDTH_32:
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*(uint32_t *)ptr = (uint32_t)val64;
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break;
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case VMX_VMCS_FIELD_WIDTH_64:
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if (!!VMX_VMCS_FIELD_ACCESS_HIGH(field)) {
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*(uint32_t *)ptr = (uint32_t)val64;
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} else {
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*ptr = val64;
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}
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break;
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case VMX_VMCS_FIELD_WIDTH_NATURAL:
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default:
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*ptr = val64;
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break;
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}
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}
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void nested_vmx_result(enum VMXResult result, int error_number)
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{
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uint64_t rflags = exec_vmread(VMX_GUEST_RFLAGS);
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@ -495,10 +643,16 @@ int32_t vmxoff_vmexit_handler(struct acrn_vcpu *vcpu)
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* @pre vcpu != NULL
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* @pre vmcs02 is current
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*/
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static void sync_vmcs02_to_vmcs12(__unused struct acrn_vcpu *vcpu)
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static void sync_vmcs02_to_vmcs12(struct acrn_vcpu *vcpu)
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{
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/* Implemented in next patch */
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return;
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uint64_t vmcs12 = (uint64_t)&vcpu->arch.nested.vmcs12;
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uint64_t val64;
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uint32_t idx;
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for (idx = 0; idx < MAX_SHADOW_VMCS_FIELDS; idx++) {
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val64 = exec_vmread(vmcs_shadowing_fields[idx]);
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vmcs12_write_field(vmcs12, vmcs_shadowing_fields[idx], val64);
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}
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}
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/**
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@ -507,10 +661,20 @@ static void sync_vmcs02_to_vmcs12(__unused struct acrn_vcpu *vcpu)
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* @pre vcpu != NULL
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* @pre vmcs02 is current
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*/
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static void sync_vmcs12_to_vmcs02(__unused struct acrn_vcpu *vcpu)
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static void sync_vmcs12_to_vmcs02(struct acrn_vcpu *vcpu)
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{
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/* Implemented in next patch */
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return;
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uint64_t vmcs12 = (uint64_t)&vcpu->arch.nested.vmcs12;
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uint64_t val64;
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uint32_t idx;
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for (idx = 0; idx < MAX_SHADOW_VMCS_FIELDS; idx++) {
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val64 = vmcs12_read_field(vmcs12, vmcs_shadowing_fields[idx]);
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exec_vmwrite(vmcs_shadowing_fields[idx], val64);
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}
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/* Sync VMCS fields that are not shadowing */
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val64 = vmcs12_read_field(vmcs12, VMX_MSR_BITMAP_FULL);
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exec_vmwrite(VMX_MSR_BITMAP_FULL, gpa2hpa(vcpu->vm, val64));
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}
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/*
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@ -45,6 +45,20 @@ union value_64 {
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MSR_IA32_VMX_VMFUNC, \
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MSR_IA32_VMX_PROCBASED_CTLS3
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/* refer to ISDM APPENDIX B: FIELD ENCODING IN VMCS */
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#define VMX_VMCS_FIELD_ACCESS_HIGH(v) (((v) >> 0U) & 0x1U)
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#define VMX_VMCS_FIELD_INDEX(v) (((v) >> 1U) & 0x1ffU)
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#define VMX_VMCS_FIELD_TYPE(v) (((v) >> 10U) & 0x3U)
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#define VMX_VMCS_FIELD_TYPE_CTL (0U)
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#define VMX_VMCS_FIELD_TYPE_VMEXIT (1U)
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#define VMX_VMCS_FIELD_TYPE_GUEST (2U)
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#define VMX_VMCS_FIELD_TYPE_HOST (3U)
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#define VMX_VMCS_FIELD_WIDTH(v) (((v) >> 13U) & 0x3U)
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#define VMX_VMCS_FIELD_WIDTH_16 (0U)
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#define VMX_VMCS_FIELD_WIDTH_64 (1U)
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#define VMX_VMCS_FIELD_WIDTH_32 (2U)
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#define VMX_VMCS_FIELD_WIDTH_NATURAL (3U)
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/*
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* VM-Exit Instruction-Information Field
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*
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@ -80,8 +94,210 @@ union value_64 {
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*/
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#define VMCS12_REVISION_ID 0x15407E12U
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/* Implemented in next patch */
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struct acrn_vmcs12 {};
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/*
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* struct acrn_vmcs12 describes the emulated VMCS for the nested guest (L2).
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*/
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struct acrn_vmcs12 {
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uint8_t vmcs_hdr[4];
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uint32_t abort;
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/*
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* Rest of the memory is used for "VMCS Data"
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* Layout of VMCS Data is non-architectural and processor
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* implemetation specific.
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*/
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uint32_t launch_state;
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/* 16-bit Control Fields */
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uint16_t vpid;
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uint16_t posted_intr_nv;
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uint16_t eptp_index;
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/* 16-bit Read-only Fields */
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uint16_t padding;
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/* 16-bit Guest-State Fields */
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uint16_t guest_es;
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uint16_t guest_cs;
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uint16_t guest_ss;
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uint16_t guest_ds;
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uint16_t guest_fs;
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uint16_t guest_gs;
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uint16_t guest_ldtr;
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uint16_t guest_tr;
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uint16_t guest_intr_status;
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uint16_t pml_index;
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/* 16-bit Host-State Fields */
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uint16_t host_es;
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uint16_t host_cs;
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uint16_t host_ss;
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uint16_t host_ds;
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uint16_t host_fs;
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uint16_t host_gs;
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uint16_t host_tr;
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/* 64-bit Control Fields */
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uint64_t io_bitmap_a;
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uint64_t io_bitmap_b;
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uint64_t msr_bitmap;
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uint64_t vm_exit_msr_store_addr;
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uint64_t vm_exit_msr_load_addr;
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uint64_t vm_entry_load_addr;
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uint64_t executive_vmcs_ptr;
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uint64_t pml_addr;
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uint64_t tsc_offset;
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uint64_t virtual_apic_addr;
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uint64_t apic_access_addr;
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uint64_t posted_interrupt_desc_addr;
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uint64_t vm_func_controls;
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uint64_t ept_pointer;
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uint64_t eoi_exit_bitmap0;
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uint64_t eoi_exit_bitmap1;
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uint64_t eoi_exit_bitmap2;
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uint64_t eoi_exit_bitmap3;
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uint64_t eptp_list_addr;
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uint64_t vmread_bitmap_addr;
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uint64_t vmwrite_bitmap_addr;
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uint64_t virt_exception_info_addr;
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uint64_t xss_exiting_bitmap;
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uint64_t encls_exiting_bitmap;
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uint64_t sub_page_permission_ptr;
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uint64_t tsc_multiplier;
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/* 64-bit Read-Only Data Fields */
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uint64_t guest_phys_addr;
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/* 64-bit Guest-State Fields */
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uint64_t vmcs_link_ptr;
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uint64_t guest_ia32_debugctl;
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uint64_t guest_ia32_pat;
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uint64_t guest_ia32_efer;
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uint64_t ia32_perf_global_ctrl;
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uint64_t guest_pdpte0;
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uint64_t guest_pdpte1;
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uint64_t guest_pdpte2;
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uint64_t guest_pdpte3;
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uint64_t guest_ia32_bndcfgs;
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uint64_t guest_ia32_rtit_ctl;
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/* 64-bit Host-State Fields */
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uint64_t host_ia32_pat;
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uint64_t host_ia32_efer;
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uint64_t host_ia32_perf_global_ctrl;
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/* 32-bit Control Fields */
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uint32_t pin_based_exec_ctrl;
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uint32_t proc_based_exec_ctrl;
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uint32_t exception_bitmap;
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uint32_t page_fault_error_code_mask;
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uint32_t page_fault_error_code_match;
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uint32_t cr3_target_count;
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uint32_t vm_exit_controls;
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uint32_t vm_exit_msr_store_count;
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uint32_t vm_exit_msr_load_count;
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uint32_t vm_entry_controls;
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uint32_t vm_entry_msr_load_count;
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uint32_t vm_entry_intr_info_field;
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uint32_t vm_entry_exception_err_code;
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uint32_t vm_entry_instr_len;
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uint32_t tpr_threshold;
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uint32_t proc_based_exec_ctrl2;
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uint32_t ple_gap;
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uint32_t ple_window;
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/* 32-bit Read-Only Data Fields */
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uint32_t vm_instr_error;
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uint32_t exit_reason;
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uint32_t vm_exit_intr_info;
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uint32_t vm_exit_intr_error_code;
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uint32_t idt_vectoring_info_field;
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uint32_t idt_vectoring_error_code;
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uint32_t vm_exit_instr_len;
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uint32_t vm_exit_instr_info;
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/* 32-bit Guest-State Fields */
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uint32_t guest_es_limit;
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uint32_t guest_cs_limit;
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uint32_t guest_ss_limit;
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uint32_t guest_ds_limit;
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uint32_t guest_fs_limit;
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uint32_t guest_gs_limit;
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uint32_t guest_ldtr_limit;
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uint32_t guest_tr_limit;
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uint32_t guest_gdtr_limit;
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uint32_t guest_idtr_limit;
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uint32_t guest_es_ar;
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uint32_t guest_cs_ar;
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uint32_t guest_ss_ar;
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uint32_t guest_ds_ar;
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uint32_t guest_fs_ar;
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uint32_t guest_gs_ar;
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uint32_t guest_ldtr_ar;
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uint32_t guest_tr_ar;
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uint32_t guest_intr_state;
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uint32_t guest_activity_state;
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uint32_t guest_smbase;
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uint32_t guest_ia32_sysenter_cs;
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uint32_t vmx_preempt_timer_val;
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/* 32-bit Host-State Fields */
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uint32_t host_ia32_sysenter_cs;
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/* Natural-width Control Fields */
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uint64_t cr0_guest_host_mask;
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uint64_t cr4_guest_host_mask;
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uint64_t cr0_read_shadow;
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uint64_t cr4_read_shadow;
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uint64_t cr3_target_val0;
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uint64_t cr3_target_val1;
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uint64_t cr3_target_val2;
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uint64_t cr3_target_val3;
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/* Natural-width Read-Only Data Fields */
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uint64_t exit_qual;
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uint64_t io_rcx;
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uint64_t io_rsi;
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uint64_t io_rdi;
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uint64_t io_rip;
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uint64_t guest_linear_addr;
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/* Natural-width Guest-State Fields */
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uint64_t guest_cr0;
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uint64_t guest_cr3;
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uint64_t guest_cr4;
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uint64_t guest_es_base;
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uint64_t guest_cs_base;
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||||
uint64_t guest_ss_base;
|
||||
uint64_t guest_ds_base;
|
||||
uint64_t guest_fs_base;
|
||||
uint64_t guest_gs_base;
|
||||
uint64_t guest_ldtr_base;
|
||||
uint64_t guest_tr_base;
|
||||
uint64_t guest_gdtr_base;
|
||||
uint64_t guest_idtr_base;
|
||||
uint64_t guest_dr7;
|
||||
uint64_t guest_rsp;
|
||||
uint64_t guest_rip;
|
||||
uint64_t guest_rflags;
|
||||
uint64_t guest_pending_debug_excp;
|
||||
uint64_t guest_ia32_sysenter_esp;
|
||||
uint64_t guest_ia32_sysenter_eip;
|
||||
|
||||
/** Natural-width Host-State Fields */
|
||||
uint64_t host_cr0;
|
||||
uint64_t host_cr3;
|
||||
uint64_t host_cr4;
|
||||
uint64_t host_fs_base;
|
||||
uint64_t host_gs_base;
|
||||
uint64_t host_tr_base;
|
||||
uint64_t host_gdtr_base;
|
||||
uint64_t host_idtr_base;
|
||||
uint64_t host_ia32_sysenter_esp;
|
||||
uint64_t host_ia32_sysenter_eip;
|
||||
uint64_t host_rsp;
|
||||
uint64_t host_rip;
|
||||
};
|
||||
|
||||
enum VMXResult {
|
||||
VMsucceed,
|
||||
@ -96,6 +312,8 @@ int32_t vmptrld_vmexit_handler(struct acrn_vcpu *vcpu);
|
||||
#ifdef CONFIG_NVMX_ENABLED
|
||||
struct acrn_nested {
|
||||
uint8_t vmcs02[PAGE_SIZE]; /* VMCS to run L2 and as Link Pointer in VMCS01 */
|
||||
|
||||
/* TODO: change this to uint8_t vmcs12[PAGE_SIZE] */
|
||||
struct acrn_vmcs12 vmcs12; /* To cache L1's VMCS12*/
|
||||
uint64_t current_vmcs12_ptr; /* GPA */
|
||||
uint64_t vmxon_ptr; /* GPA */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user