mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-26 07:21:37 +00:00
irq: convert irq/vector numbers to unsigned
Currently irq and vector numbers are used inconsistently.
* Sometimes vector or irq ids is used in bit operations, indicating
that they should be unsigned (which is required by MISRA C).
* At the same time we use -1 to indicate an unknown irq (in
common_register_handler()) or unavailable irq (in
alloc_irq()). Also (irq < 0) or (vector < 0) are used for error
checking. These indicate that irq or vector ids should be signed.
This patch converts irq and vector numbers to unsigned 32-bit integers, and
replace the previous -1 with IRQ_INVALID or VECTOR_INVALID. The branch
conditions are updated accordingly.
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Junjie Mao
lijinxia
parent
5e2c83f395
commit
8c4a5987e3
@ -308,7 +308,7 @@ ptdev_update_irq_handler(struct vm *vm, struct ptdev_remapping_info *entry)
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/* active intr with irq registering */
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static struct ptdev_remapping_info *
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ptdev_activate_entry(struct ptdev_remapping_info *entry, int phys_irq,
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ptdev_activate_entry(struct ptdev_remapping_info *entry, uint32_t phys_irq,
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bool lowpri)
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{
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struct dev_handler_node *node;
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@ -350,7 +350,7 @@ static bool ptdev_hv_owned_intx(struct vm *vm, struct ptdev_intx_info *info)
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}
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static void ptdev_build_physical_msi(struct vm *vm, struct ptdev_msi_info *info,
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int vector)
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uint32_t vector)
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{
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uint64_t vdmask, pdmask;
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uint32_t dest, delmode;
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@ -785,7 +785,7 @@ int ptdev_msix_remap(struct vm *vm, uint16_t virt_bdf,
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if (!is_entry_active(entry)) {
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/* update msi source and active entry */
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ptdev_activate_entry(entry, -1, lowpri);
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ptdev_activate_entry(entry, IRQ_INVALID, lowpri);
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}
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/* build physical config MSI, update to info->pmsi_xxx */
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@ -854,7 +854,7 @@ int ptdev_intx_pin_remap(struct vm *vm, struct ptdev_intx_info *info)
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{
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struct ptdev_remapping_info *entry;
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uint64_t rte;
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int phys_irq;
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uint32_t phys_irq;
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int phys_pin;
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bool lowpri = !is_vm0(vm);
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bool need_switch_vpin_src = false;
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@ -1088,7 +1088,7 @@ void ptdev_release_all_entries(struct vm *vm)
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}
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static void get_entry_info(struct ptdev_remapping_info *entry, char *type,
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int *irq, int *vector, uint64_t *dest, bool *lvl_tm,
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uint32_t *irq, uint32_t *vector, uint64_t *dest, bool *lvl_tm,
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int *pin, int *vpin, int *bdf, int *vbdf)
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{
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if (is_entry_active(entry)) {
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@ -1101,7 +1101,7 @@ static void get_entry_info(struct ptdev_remapping_info *entry, char *type,
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*lvl_tm = true;
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else
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*lvl_tm = false;
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*pin = -1;
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*pin = IRQ_INVALID;
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*vpin = -1;
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*bdf = entry->phys_bdf;
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*vbdf = entry->virt_bdf;
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@ -1130,7 +1130,7 @@ static void get_entry_info(struct ptdev_remapping_info *entry, char *type,
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*vector = dev_to_vector(entry->node);
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} else {
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strcpy_s(type, 16, "NONE");
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*irq = -1;
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*irq = IRQ_INVALID;
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*vector = 0;
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*dest = 0;
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*lvl_tm = 0;
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@ -1144,7 +1144,8 @@ static void get_entry_info(struct ptdev_remapping_info *entry, char *type,
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int get_ptdev_info(char *str, int str_max)
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{
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struct ptdev_remapping_info *entry;
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int len, size = str_max, irq, vector;
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int len, size = str_max;
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uint32_t irq, vector;
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char type[16];
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uint64_t dest;
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bool lvl_tm;
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@ -99,7 +99,7 @@ int create_vcpu(int cpu_id, struct vm *vm, struct vcpu **rtn_vcpu_handle)
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memset(vcpu->arch_vcpu.vmcs, 0, CPU_PAGE_SIZE);
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/* Initialize exception field in VCPU context */
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vcpu->arch_vcpu.exception_info.exception = -1;
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vcpu->arch_vcpu.exception_info.exception = VECTOR_INVALID;
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/* Initialize cur context */
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vcpu->arch_vcpu.cur_context = NORMAL_WORLD;
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@ -137,11 +137,11 @@ enum irqstate {
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};
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static int
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vioapic_set_irqstate(struct vm *vm, int irq, enum irqstate irqstate)
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vioapic_set_irqstate(struct vm *vm, uint32_t irq, enum irqstate irqstate)
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{
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struct vioapic *vioapic;
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if (irq < 0 || irq >= vioapic_pincount(vm))
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if (irq >= (uint32_t)vioapic_pincount(vm))
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return -EINVAL;
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vioapic = vm_ioapic(vm);
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@ -167,19 +167,19 @@ vioapic_set_irqstate(struct vm *vm, int irq, enum irqstate irqstate)
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}
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int
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vioapic_assert_irq(struct vm *vm, int irq)
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vioapic_assert_irq(struct vm *vm, uint32_t irq)
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{
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return vioapic_set_irqstate(vm, irq, IRQSTATE_ASSERT);
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}
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int
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vioapic_deassert_irq(struct vm *vm, int irq)
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vioapic_deassert_irq(struct vm *vm, uint32_t irq)
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{
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return vioapic_set_irqstate(vm, irq, IRQSTATE_DEASSERT);
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}
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int
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vioapic_pulse_irq(struct vm *vm, int irq)
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vioapic_pulse_irq(struct vm *vm, uint32_t irq)
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{
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return vioapic_set_irqstate(vm, irq, IRQSTATE_PULSE);
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}
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@ -258,7 +258,7 @@ vioapic_read(struct vioapic *vioapic, uint32_t addr)
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* register to clear related IRR.
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*/
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static void
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vioapic_write_eoi(struct vioapic *vioapic, int32_t vector)
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vioapic_write_eoi(struct vioapic *vioapic, uint32_t vector)
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{
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struct vm *vm = vioapic->vm;
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int pin;
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@ -477,7 +477,7 @@ vioapic_mmio_write(void *vm, uint64_t gpa, uint64_t wval,
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}
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void
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vioapic_process_eoi(struct vm *vm, int vector)
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vioapic_process_eoi(struct vm *vm, uint32_t vector)
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{
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struct vioapic *vioapic;
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int pin;
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@ -83,13 +83,13 @@ do { \
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static void *apicv_apic_access_addr;
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static int
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apicv_set_intr_ready(struct vlapic *vlapic, int vector, bool level);
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apicv_set_intr_ready(struct vlapic *vlapic, uint32_t vector, bool level);
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static int
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apicv_pending_intr(struct vlapic *vlapic, int *vecptr);
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apicv_pending_intr(struct vlapic *vlapic, uint32_t *vecptr);
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static void
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apicv_set_tmr(struct vlapic *vlapic, int vector, bool level);
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apicv_set_tmr(struct vlapic *vlapic, uint32_t vector, bool level);
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static void
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apicv_batch_set_tmr(struct vlapic *vlapic);
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@ -366,14 +366,14 @@ vlapic_esr_write_handler(struct vlapic *vlapic)
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* Returns 1 if the vcpu needs to be notified of the interrupt and 0 otherwise.
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*/
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static int
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vlapic_set_intr_ready(struct vlapic *vlapic, int vector, bool level)
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vlapic_set_intr_ready(struct vlapic *vlapic, uint32_t vector, bool level)
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{
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struct lapic *lapic;
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struct lapic_reg *irrptr, *tmrptr;
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uint32_t mask;
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int idx;
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ASSERT((vector >= 0) && (vector <= NR_MAX_VECTOR),
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ASSERT(vector <= NR_MAX_VECTOR,
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"invalid vector %d", vector);
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lapic = vlapic->apic_page;
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@ -742,7 +742,7 @@ vlapic_set_error(struct vlapic *vlapic, uint32_t mask)
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}
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static int
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vlapic_trigger_lvt(struct vlapic *vlapic, int vector)
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vlapic_trigger_lvt(struct vlapic *vlapic, uint32_t vector)
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{
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uint32_t lvt;
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@ -1081,7 +1081,7 @@ vlapic_icrlo_write_handler(struct vlapic *vlapic)
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}
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int
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vlapic_pending_intr(struct vlapic *vlapic, int *vecptr)
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vlapic_pending_intr(struct vlapic *vlapic, uint32_t *vecptr)
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{
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struct lapic *lapic = vlapic->apic_page;
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int i, bitpos;
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@ -1111,7 +1111,7 @@ vlapic_pending_intr(struct vlapic *vlapic, int *vecptr)
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}
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void
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vlapic_intr_accepted(struct vlapic *vlapic, int vector)
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vlapic_intr_accepted(struct vlapic *vlapic, uint32_t vector)
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{
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struct lapic *lapic = vlapic->apic_page;
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struct lapic_reg *irrptr, *isrptr;
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@ -1584,7 +1584,7 @@ vlapic_enabled(struct vlapic *vlapic)
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}
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void
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vlapic_set_tmr(struct vlapic *vlapic, int vector, bool level)
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vlapic_set_tmr(struct vlapic *vlapic, uint32_t vector, bool level)
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{
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struct lapic *lapic;
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struct lapic_reg *tmrptr;
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@ -1613,7 +1613,7 @@ vlapic_apicv_batch_set_tmr(struct vlapic *vlapic)
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}
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void
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vlapic_apicv_set_tmr(struct vlapic *vlapic, int vector, bool level)
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vlapic_apicv_set_tmr(struct vlapic *vlapic, uint32_t vector, bool level)
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{
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if (vlapic->ops.apicv_set_tmr != NULL)
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vlapic->ops.apicv_set_tmr(vlapic, vector, level);
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@ -1622,7 +1622,7 @@ vlapic_apicv_set_tmr(struct vlapic *vlapic, int vector, bool level)
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void
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vlapic_reset_tmr(struct vlapic *vlapic)
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{
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int vector;
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uint32_t vector;
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dev_dbg(ACRN_DBG_LAPIC,
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"vlapic resetting all vectors to edge-triggered");
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@ -1635,9 +1635,9 @@ vlapic_reset_tmr(struct vlapic *vlapic)
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void
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vlapic_set_tmr_one_vec(struct vlapic *vlapic, __unused int delmode,
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int vector, bool level)
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uint32_t vector, bool level)
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{
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ASSERT((vector >= 0) && (vector <= NR_MAX_VECTOR),
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ASSERT(vector <= NR_MAX_VECTOR,
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"invalid vector %d", vector);
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/*
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@ -1662,7 +1662,7 @@ vlapic_set_tmr_one_vec(struct vlapic *vlapic, __unused int delmode,
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}
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int
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vlapic_set_intr(struct vcpu *vcpu, int vector, bool level)
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vlapic_set_intr(struct vcpu *vcpu, uint32_t vector, bool level)
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{
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struct vlapic *vlapic;
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int ret = 0;
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@ -1687,7 +1687,7 @@ vlapic_set_intr(struct vcpu *vcpu, int vector, bool level)
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}
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int
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vlapic_set_local_intr(struct vm *vm, int cpu_id, int vector)
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vlapic_set_local_intr(struct vm *vm, int cpu_id, uint32_t vector)
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{
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struct vlapic *vlapic;
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uint64_t dmask = 0;
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@ -2013,7 +2013,7 @@ void vlapic_free(struct vcpu *vcpu)
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* APIC-v functions
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* **/
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static int
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apicv_set_intr_ready(struct vlapic *vlapic, int vector, __unused bool level)
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apicv_set_intr_ready(struct vlapic *vlapic, uint32_t vector, __unused bool level)
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{
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struct pir_desc *pir_desc;
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uint64_t mask;
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@ -2030,7 +2030,7 @@ apicv_set_intr_ready(struct vlapic *vlapic, int vector, __unused bool level)
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}
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static int
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apicv_pending_intr(struct vlapic *vlapic, __unused int *vecptr)
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apicv_pending_intr(struct vlapic *vlapic, __unused uint32_t *vecptr)
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{
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struct pir_desc *pir_desc;
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struct lapic *lapic;
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@ -2061,7 +2061,7 @@ apicv_pending_intr(struct vlapic *vlapic, __unused int *vecptr)
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}
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static void
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apicv_set_tmr(__unused struct vlapic *vlapic, int vector, bool level)
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apicv_set_tmr(__unused struct vlapic *vlapic, uint32_t vector, bool level)
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{
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uint64_t mask, val;
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@ -2234,7 +2234,7 @@ int veoi_vmexit_handler(struct vcpu *vcpu)
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{
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struct vlapic *vlapic = NULL;
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int vector;
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uint32_t vector;
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struct lapic *lapic;
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struct lapic_reg *tmrptr;
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uint32_t idx, mask;
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@ -99,11 +99,11 @@ struct pir_desc {
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struct vlapic_ops {
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int (*apicv_set_intr_ready)
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(struct vlapic *vlapic, int vector, bool level);
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int (*apicv_pending_intr)(struct vlapic *vlapic, int *vecptr);
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void (*apicv_intr_accepted)(struct vlapic *vlapic, int vector);
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(struct vlapic *vlapic, uint32_t vector, bool level);
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int (*apicv_pending_intr)(struct vlapic *vlapic, uint32_t *vecptr);
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void (*apicv_intr_accepted)(struct vlapic *vlapic, uint32_t vector);
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void (*apicv_post_intr)(struct vlapic *vlapic, int hostcpu);
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void (*apicv_set_tmr)(struct vlapic *vlapic, int vector, bool level);
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void (*apicv_set_tmr)(struct vlapic *vlapic, uint32_t vector, bool level);
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void (*apicv_batch_set_tmr)(struct vlapic *vlapic);
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void (*enable_x2apic_mode)(struct vlapic *vlapic);
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};
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@ -58,7 +58,7 @@ struct pic {
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bool rotate;
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bool sfn; /* special fully-nested mode */
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int irq_base;
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uint32_t irq_base;
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uint8_t request; /* Interrupt Request Register (IIR) */
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uint8_t service; /* Interrupt Service (ISR) */
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uint8_t mask; /* Interrupt Mask Register (IMR) */
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@ -489,12 +489,12 @@ static void vpic_set_pinstate(struct vpic *vpic, int pin, bool newstate)
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vpic_notify_intr(vpic);
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}
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static int vpic_set_irqstate(struct vm *vm, int irq, enum irqstate irqstate)
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static int vpic_set_irqstate(struct vm *vm, uint32_t irq, enum irqstate irqstate)
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{
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struct vpic *vpic;
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struct pic *pic;
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if (irq < 0 || irq > 15)
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if (irq > 15)
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return -EINVAL;
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vpic = vm_pic(vm);
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@ -524,26 +524,26 @@ static int vpic_set_irqstate(struct vm *vm, int irq, enum irqstate irqstate)
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}
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/* hypervisor interface: assert/deassert/pulse irq */
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int vpic_assert_irq(struct vm *vm, int irq)
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int vpic_assert_irq(struct vm *vm, uint32_t irq)
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{
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return vpic_set_irqstate(vm, irq, IRQSTATE_ASSERT);
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}
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int vpic_deassert_irq(struct vm *vm, int irq)
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int vpic_deassert_irq(struct vm *vm, uint32_t irq)
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{
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return vpic_set_irqstate(vm, irq, IRQSTATE_DEASSERT);
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}
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int vpic_pulse_irq(struct vm *vm, int irq)
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int vpic_pulse_irq(struct vm *vm, uint32_t irq)
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{
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return vpic_set_irqstate(vm, irq, IRQSTATE_PULSE);
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}
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int vpic_set_irq_trigger(struct vm *vm, int irq, enum vpic_trigger trigger)
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int vpic_set_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger trigger)
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{
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struct vpic *vpic;
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if (irq < 0 || irq > 15)
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if (irq > 15)
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return -EINVAL;
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/*
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@ -575,11 +575,11 @@ int vpic_set_irq_trigger(struct vm *vm, int irq, enum vpic_trigger trigger)
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return 0;
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}
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int vpic_get_irq_trigger(struct vm *vm, int irq, enum vpic_trigger *trigger)
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int vpic_get_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger *trigger)
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{
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struct vpic *vpic;
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if (irq < 0 || irq > 15)
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if (irq > 15)
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return -EINVAL;
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vpic = vm_pic(vm);
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@ -593,7 +593,7 @@ int vpic_get_irq_trigger(struct vm *vm, int irq, enum vpic_trigger *trigger)
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return 0;
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}
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void vpic_pending_intr(struct vm *vm, int *vecptr)
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void vpic_pending_intr(struct vm *vm, uint32_t *vecptr)
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{
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struct vpic *vpic;
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struct pic *pic;
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@ -616,7 +616,7 @@ void vpic_pending_intr(struct vm *vm, int *vecptr)
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* interrupt vector instead.
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*/
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if (pin == -1) {
|
||||
*vecptr = -1;
|
||||
*vecptr = VECTOR_INVALID;
|
||||
VPIC_UNLOCK(vpic);
|
||||
return;
|
||||
}
|
||||
@ -646,7 +646,7 @@ static void vpic_pin_accepted(struct pic *pic, int pin)
|
||||
}
|
||||
}
|
||||
|
||||
void vpic_intr_accepted(struct vm *vm, int vector)
|
||||
void vpic_intr_accepted(struct vm *vm, uint32_t vector)
|
||||
{
|
||||
struct vpic *vpic;
|
||||
int pin;
|
||||
|
||||
@ -76,7 +76,7 @@ static int is_guest_irq_enabled(struct vcpu *vcpu)
|
||||
static bool vcpu_pending_request(struct vcpu *vcpu)
|
||||
{
|
||||
struct vlapic *vlapic;
|
||||
int vector = 0;
|
||||
uint32_t vector = 0;
|
||||
int ret = 0;
|
||||
|
||||
/* Query vLapic to get vector to inject */
|
||||
@ -115,7 +115,7 @@ int vcpu_make_request(struct vcpu *vcpu, int eventid)
|
||||
static int vcpu_do_pending_event(struct vcpu *vcpu)
|
||||
{
|
||||
struct vlapic *vlapic = vcpu->arch_vcpu.vlapic;
|
||||
int vector = 0;
|
||||
uint32_t vector = 0;
|
||||
int ret = 0;
|
||||
|
||||
if (is_vapic_intr_delivery_supported()) {
|
||||
@ -152,7 +152,7 @@ static int vcpu_do_pending_extint(struct vcpu *vcpu)
|
||||
{
|
||||
struct vm *vm;
|
||||
struct vcpu *primary;
|
||||
int vector;
|
||||
uint32_t vector;
|
||||
|
||||
vm = vcpu->vm;
|
||||
|
||||
@ -162,7 +162,7 @@ static int vcpu_do_pending_extint(struct vcpu *vcpu)
|
||||
if (vm->vpic && vcpu == primary) {
|
||||
|
||||
vpic_pending_intr(vcpu->vm, &vector);
|
||||
if (vector > 0) {
|
||||
if (vector <= NR_MAX_VECTOR) {
|
||||
dev_dbg(ACRN_DBG_INTR, "VPIC: to inject PIC vector %d\n",
|
||||
vector & 0xFF);
|
||||
exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD,
|
||||
@ -192,7 +192,7 @@ void dump_lapic(void)
|
||||
}
|
||||
|
||||
/* SDM Vol3 -6.15, Table 6-4 - interrupt and exception classes */
|
||||
static int get_excep_class(int32_t vector)
|
||||
static int get_excep_class(uint32_t vector)
|
||||
{
|
||||
if (vector == IDT_DE || vector == IDT_TS || vector == IDT_NP ||
|
||||
vector == IDT_SS || vector == IDT_GP)
|
||||
@ -203,35 +203,34 @@ static int get_excep_class(int32_t vector)
|
||||
return EXCEPTION_CLASS_BENIGN;
|
||||
}
|
||||
|
||||
int vcpu_queue_exception(struct vcpu *vcpu, int32_t vector,
|
||||
int vcpu_queue_exception(struct vcpu *vcpu, uint32_t vector,
|
||||
uint32_t err_code)
|
||||
{
|
||||
/* VECTOR_INVALID is also greater than 32 */
|
||||
if (vector >= 32) {
|
||||
pr_err("invalid exception vector %d", vector);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (vcpu->arch_vcpu.exception_info.exception >= 0) {
|
||||
int32_t prev_vector =
|
||||
vcpu->arch_vcpu.exception_info.exception;
|
||||
int32_t new_class, prev_class;
|
||||
int32_t prev_vector =
|
||||
vcpu->arch_vcpu.exception_info.exception;
|
||||
int32_t new_class, prev_class;
|
||||
|
||||
/* SDM vol3 - 6.15, Table 6-5 - conditions for generating a
|
||||
* double fault */
|
||||
prev_class = get_excep_class(prev_vector);
|
||||
new_class = get_excep_class(vector);
|
||||
if (prev_vector == IDT_DF &&
|
||||
new_class != EXCEPTION_CLASS_BENIGN) {
|
||||
/* triple fault happen - shutdwon mode */
|
||||
return vcpu_make_request(vcpu, ACRN_REQUEST_TRP_FAULT);
|
||||
} else if ((prev_class == EXCEPTION_CLASS_CONT &&
|
||||
new_class == EXCEPTION_CLASS_CONT) ||
|
||||
(prev_class == EXCEPTION_CLASS_PF &&
|
||||
new_class != EXCEPTION_CLASS_BENIGN)) {
|
||||
/* generate double fault */
|
||||
vector = IDT_DF;
|
||||
err_code = 0;
|
||||
}
|
||||
/* SDM vol3 - 6.15, Table 6-5 - conditions for generating a
|
||||
* double fault */
|
||||
prev_class = get_excep_class(prev_vector);
|
||||
new_class = get_excep_class(vector);
|
||||
if (prev_vector == IDT_DF &&
|
||||
new_class != EXCEPTION_CLASS_BENIGN) {
|
||||
/* triple fault happen - shutdwon mode */
|
||||
return vcpu_make_request(vcpu, ACRN_REQUEST_TRP_FAULT);
|
||||
} else if ((prev_class == EXCEPTION_CLASS_CONT &&
|
||||
new_class == EXCEPTION_CLASS_CONT) ||
|
||||
(prev_class == EXCEPTION_CLASS_PF &&
|
||||
new_class != EXCEPTION_CLASS_BENIGN)) {
|
||||
/* generate double fault */
|
||||
vector = IDT_DF;
|
||||
err_code = 0;
|
||||
}
|
||||
|
||||
vcpu->arch_vcpu.exception_info.exception = vector;
|
||||
@ -254,12 +253,12 @@ static void _vcpu_inject_exception(struct vcpu *vcpu, uint32_t vector)
|
||||
exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD, VMX_INT_INFO_VALID |
|
||||
(exception_type[vector] << 8) | (vector & 0xFF));
|
||||
|
||||
vcpu->arch_vcpu.exception_info.exception = -1;
|
||||
vcpu->arch_vcpu.exception_info.exception = VECTOR_INVALID;
|
||||
}
|
||||
|
||||
static int vcpu_inject_hi_exception(struct vcpu *vcpu)
|
||||
{
|
||||
int vector = vcpu->arch_vcpu.exception_info.exception;
|
||||
uint32_t vector = vcpu->arch_vcpu.exception_info.exception;
|
||||
|
||||
if (vector == IDT_MC || vector == IDT_BP || vector == IDT_DB) {
|
||||
_vcpu_inject_exception(vcpu, vector);
|
||||
@ -271,10 +270,10 @@ static int vcpu_inject_hi_exception(struct vcpu *vcpu)
|
||||
|
||||
static int vcpu_inject_lo_exception(struct vcpu *vcpu)
|
||||
{
|
||||
int vector = vcpu->arch_vcpu.exception_info.exception;
|
||||
uint32_t vector = vcpu->arch_vcpu.exception_info.exception;
|
||||
|
||||
/* high priority exception already be injected */
|
||||
if (vector >= 0) {
|
||||
if (vector <= NR_MAX_VECTOR) {
|
||||
_vcpu_inject_exception(vcpu, vector);
|
||||
return 1;
|
||||
}
|
||||
@ -486,7 +485,7 @@ void cancel_event_injection(struct vcpu *vcpu)
|
||||
int exception_vmexit_handler(struct vcpu *vcpu)
|
||||
{
|
||||
uint32_t intinfo, int_err_code = 0;
|
||||
int32_t exception_vector = -1;
|
||||
uint32_t exception_vector = VECTOR_INVALID;
|
||||
uint32_t cpl;
|
||||
int status = 0;
|
||||
|
||||
|
||||
@ -22,7 +22,7 @@ struct gsi_table {
|
||||
void *addr;
|
||||
};
|
||||
static struct gsi_table gsi_table[NR_MAX_GSI];
|
||||
static int nr_gsi;
|
||||
static uint32_t nr_gsi;
|
||||
static spinlock_t ioapic_lock;
|
||||
|
||||
/*
|
||||
@ -144,7 +144,7 @@ ioapic_set_rte_entry(void *ioapic_addr,
|
||||
}
|
||||
|
||||
static inline struct ioapic_rte
|
||||
create_rte_for_legacy_irq(int irq, int vr)
|
||||
create_rte_for_legacy_irq(uint32_t irq, uint32_t vr)
|
||||
{
|
||||
struct ioapic_rte rte = {0, 0};
|
||||
|
||||
@ -169,7 +169,7 @@ create_rte_for_legacy_irq(int irq, int vr)
|
||||
}
|
||||
|
||||
static inline struct ioapic_rte
|
||||
create_rte_for_gsi_irq(int irq, int vr)
|
||||
create_rte_for_gsi_irq(uint32_t irq, uint32_t vr)
|
||||
{
|
||||
struct ioapic_rte rte = {0, 0};
|
||||
|
||||
@ -192,7 +192,7 @@ create_rte_for_gsi_irq(int irq, int vr)
|
||||
return rte;
|
||||
}
|
||||
|
||||
static void ioapic_set_routing(int gsi, int vr)
|
||||
static void ioapic_set_routing(uint32_t gsi, uint32_t vr)
|
||||
{
|
||||
void *addr;
|
||||
struct ioapic_rte rte;
|
||||
@ -211,7 +211,7 @@ static void ioapic_set_routing(int gsi, int vr)
|
||||
rte.lo_32);
|
||||
}
|
||||
|
||||
void ioapic_get_rte(int irq, uint64_t *rte)
|
||||
void ioapic_get_rte(uint32_t irq, uint64_t *rte)
|
||||
{
|
||||
void *addr;
|
||||
struct ioapic_rte _rte;
|
||||
@ -226,7 +226,7 @@ void ioapic_get_rte(int irq, uint64_t *rte)
|
||||
*rte = *rte << 32 | _rte.lo_32;
|
||||
}
|
||||
|
||||
void ioapic_set_rte(int irq, uint64_t raw_rte)
|
||||
void ioapic_set_rte(uint32_t irq, uint64_t raw_rte)
|
||||
{
|
||||
void *addr;
|
||||
struct ioapic_rte rte;
|
||||
@ -244,17 +244,17 @@ void ioapic_set_rte(int irq, uint64_t raw_rte)
|
||||
rte.lo_32);
|
||||
}
|
||||
|
||||
int irq_gsi_num(void)
|
||||
uint32_t irq_gsi_num(void)
|
||||
{
|
||||
return nr_gsi;
|
||||
}
|
||||
|
||||
bool irq_is_gsi(int irq)
|
||||
bool irq_is_gsi(uint32_t irq)
|
||||
{
|
||||
return irq < nr_gsi;
|
||||
}
|
||||
|
||||
int irq_to_pin(int irq)
|
||||
int irq_to_pin(uint32_t irq)
|
||||
{
|
||||
if (irq_is_gsi(irq))
|
||||
return gsi_table[irq].pin;
|
||||
@ -262,9 +262,9 @@ int irq_to_pin(int irq)
|
||||
return -1;
|
||||
}
|
||||
|
||||
int pin_to_irq(int pin)
|
||||
uint32_t pin_to_irq(int pin)
|
||||
{
|
||||
int i;
|
||||
uint32_t i;
|
||||
|
||||
if (pin < 0)
|
||||
return IRQ_INVALID;
|
||||
@ -277,7 +277,7 @@ int pin_to_irq(int pin)
|
||||
}
|
||||
|
||||
void
|
||||
irq_gsi_mask_unmask(int irq, bool mask)
|
||||
irq_gsi_mask_unmask(uint32_t irq, bool mask)
|
||||
{
|
||||
void *addr = gsi_table[irq].addr;
|
||||
int pin = gsi_table[irq].pin;
|
||||
@ -299,7 +299,7 @@ irq_gsi_mask_unmask(int irq, bool mask)
|
||||
void setup_ioapic_irq(void)
|
||||
{
|
||||
int ioapic_id;
|
||||
int gsi;
|
||||
uint32_t gsi;
|
||||
int vr;
|
||||
|
||||
spinlock_init(&ioapic_lock);
|
||||
@ -328,7 +328,7 @@ void setup_ioapic_irq(void)
|
||||
gsi_table[gsi].pin = pin;
|
||||
|
||||
/* pinned irq before use it */
|
||||
if (irq_mark_used(gsi) < 0) {
|
||||
if (irq_mark_used(gsi) > NR_MAX_IRQS) {
|
||||
pr_err("failed to alloc IRQ[%d]", gsi);
|
||||
gsi++;
|
||||
continue;
|
||||
@ -359,7 +359,7 @@ void setup_ioapic_irq(void)
|
||||
|
||||
void dump_ioapic(void)
|
||||
{
|
||||
int irq;
|
||||
uint32_t irq;
|
||||
|
||||
for (irq = 0; irq < nr_gsi; irq++) {
|
||||
void *addr = gsi_table[irq].addr;
|
||||
@ -386,7 +386,7 @@ void get_rte_info(struct ioapic_rte *rte, bool *mask, bool *irr,
|
||||
|
||||
int get_ioapic_info(char *str, int str_max_len)
|
||||
{
|
||||
int irq, len, size = str_max_len;
|
||||
uint32_t irq, len, size = str_max_len;
|
||||
|
||||
len = snprintf(str, size,
|
||||
"\r\nIRQ\tPIN\tRTE.HI32\tRTE.LO32\tVEC\tDST\tDM\tTM\tDELM\tIRR\tMASK");
|
||||
|
||||
@ -10,9 +10,9 @@ static spinlock_t exception_spinlock = { .head = 0, .tail = 0, };
|
||||
|
||||
struct irq_request_info {
|
||||
/* vector set to 0xE0 ~ 0xFF for pri_register_handler
|
||||
* and set to -1 for normal_register_handler
|
||||
* and set to VECTOR_INVALID for normal_register_handler
|
||||
*/
|
||||
int vector;
|
||||
uint32_t vector;
|
||||
dev_handler_t func;
|
||||
void *dev_data;
|
||||
bool share;
|
||||
@ -22,10 +22,10 @@ struct irq_request_info {
|
||||
|
||||
/* any field change in below required irq_lock protection with irqsave */
|
||||
struct irq_desc {
|
||||
int irq; /* index to irq_desc_base */
|
||||
uint32_t irq; /* index to irq_desc_base */
|
||||
enum irq_state used; /* this irq have assigned to device */
|
||||
enum irq_desc_state state; /* irq_desc status */
|
||||
int vector; /* assigned vector */
|
||||
uint32_t vector; /* assigned vector */
|
||||
void *handler_data; /* irq_handler private data */
|
||||
int (*irq_handler)(struct irq_desc *irq_desc, void *handler_data);
|
||||
struct dev_handler_node *dev_list;
|
||||
@ -35,7 +35,7 @@ struct irq_desc {
|
||||
};
|
||||
|
||||
static struct irq_desc *irq_desc_base;
|
||||
static int vector_to_irq[NR_MAX_VECTOR + 1];
|
||||
static uint32_t vector_to_irq[NR_MAX_VECTOR + 1];
|
||||
|
||||
spurious_handler_t spurious_handler;
|
||||
|
||||
@ -67,9 +67,9 @@ static void init_irq_desc(void)
|
||||
* lowpri: 0x20-0x7F
|
||||
* highpri: 0x80-0xDF
|
||||
*/
|
||||
static int find_available_vector(bool lowpri)
|
||||
static uint32_t find_available_vector(bool lowpri)
|
||||
{
|
||||
int i, start, end;
|
||||
uint32_t i, start, end;
|
||||
|
||||
if (lowpri) {
|
||||
start = VECTOR_FOR_NOR_LOWPRI_START;
|
||||
@ -84,21 +84,21 @@ static int find_available_vector(bool lowpri)
|
||||
if (vector_to_irq[i] == IRQ_INVALID)
|
||||
return i;
|
||||
}
|
||||
return -1;
|
||||
return VECTOR_INVALID;
|
||||
}
|
||||
|
||||
/*
|
||||
* check and set irq to be assigned
|
||||
* return: -1 if irq already assigned otherwise return irq
|
||||
* return: IRQ_INVALID if irq already assigned otherwise return irq
|
||||
*/
|
||||
int irq_mark_used(int irq)
|
||||
uint32_t irq_mark_used(uint32_t irq)
|
||||
{
|
||||
struct irq_desc *desc;
|
||||
|
||||
spinlock_rflags;
|
||||
|
||||
if (irq < 0)
|
||||
return -1;
|
||||
if (irq > NR_MAX_IRQS)
|
||||
return IRQ_INVALID;
|
||||
|
||||
desc = irq_desc_base + irq;
|
||||
spinlock_irqsave_obtain(&desc->irq_lock);
|
||||
@ -110,11 +110,11 @@ int irq_mark_used(int irq)
|
||||
|
||||
/*
|
||||
* system find available irq and set assigned
|
||||
* return: irq, -1 not found
|
||||
* return: irq, VECTOR_INVALID not found
|
||||
*/
|
||||
static int alloc_irq(void)
|
||||
static uint32_t alloc_irq(void)
|
||||
{
|
||||
int i;
|
||||
uint32_t i;
|
||||
struct irq_desc *desc;
|
||||
|
||||
spinlock_rflags;
|
||||
@ -129,11 +129,11 @@ static int alloc_irq(void)
|
||||
}
|
||||
spinlock_irqrestore_release(&desc->irq_lock);
|
||||
}
|
||||
return (i == NR_MAX_IRQS) ? -1:i;
|
||||
return (i == NR_MAX_IRQS) ? IRQ_INVALID : i;
|
||||
}
|
||||
|
||||
/* need irq_lock protection before use */
|
||||
static void _irq_desc_set_vector(int irq, int vr)
|
||||
static void _irq_desc_set_vector(uint32_t irq, uint32_t vr)
|
||||
{
|
||||
struct irq_desc *desc;
|
||||
|
||||
@ -143,7 +143,7 @@ static void _irq_desc_set_vector(int irq, int vr)
|
||||
}
|
||||
|
||||
/* lock version of set vector */
|
||||
static void irq_desc_set_vector(int irq, int vr)
|
||||
static void irq_desc_set_vector(uint32_t irq, uint32_t vr)
|
||||
{
|
||||
struct irq_desc *desc;
|
||||
|
||||
@ -157,12 +157,12 @@ static void irq_desc_set_vector(int irq, int vr)
|
||||
}
|
||||
|
||||
/* used with holding irq_lock outside */
|
||||
static void _irq_desc_free_vector(int irq)
|
||||
static void _irq_desc_free_vector(uint32_t irq)
|
||||
{
|
||||
struct irq_desc *desc;
|
||||
int vr;
|
||||
uint32_t vr;
|
||||
|
||||
if (irq > NR_MAX_IRQS || irq < 0)
|
||||
if (irq > NR_MAX_IRQS)
|
||||
return;
|
||||
|
||||
desc = irq_desc_base + irq;
|
||||
@ -221,7 +221,7 @@ irq_desc_append_dev(struct irq_desc *desc, void *node, bool share)
|
||||
}
|
||||
|
||||
static struct dev_handler_node*
|
||||
common_register_handler(int irq,
|
||||
common_register_handler(uint32_t irq,
|
||||
struct irq_request_info *info)
|
||||
{
|
||||
struct dev_handler_node *node = NULL;
|
||||
@ -230,7 +230,7 @@ common_register_handler(int irq,
|
||||
|
||||
/* ======================================================
|
||||
* This is low level ISR handler registering function
|
||||
* case: irq = -1
|
||||
* case: irq = IRQ_INVALID
|
||||
* caller did not know which irq to use, and want system to
|
||||
* allocate available irq for it. These irq are in range:
|
||||
* nr_gsi ~ NR_MAX_IRQS
|
||||
@ -260,12 +260,12 @@ common_register_handler(int irq,
|
||||
/* HV select a irq for device if irq < 0
|
||||
* this vector/irq match to APCI DSDT or PCI INTx/MSI
|
||||
*/
|
||||
if (irq < 0)
|
||||
if (irq == IRQ_INVALID)
|
||||
irq = alloc_irq();
|
||||
else
|
||||
irq = irq_mark_used(irq);
|
||||
|
||||
if (irq < 0) {
|
||||
if (irq > NR_MAX_IRQS) {
|
||||
pr_err("failed to assign IRQ");
|
||||
goto OUT;
|
||||
}
|
||||
@ -290,7 +290,7 @@ OUT:
|
||||
if (info->vector >= VECTOR_FOR_PRI_START &&
|
||||
info->vector <= VECTOR_FOR_PRI_END)
|
||||
irq_desc_set_vector(irq, info->vector);
|
||||
else if (info->vector < 0)
|
||||
else if (info->vector > NR_MAX_VECTOR)
|
||||
irq_desc_alloc_vector(irq, info->lowpri);
|
||||
else {
|
||||
pr_err("the input vector is not correct");
|
||||
@ -314,15 +314,15 @@ OUT:
|
||||
}
|
||||
|
||||
/* it is safe to call irq_desc_alloc_vector multiple times*/
|
||||
int irq_desc_alloc_vector(int irq, bool lowpri)
|
||||
uint32_t irq_desc_alloc_vector(uint32_t irq, bool lowpri)
|
||||
{
|
||||
int vr = -1;
|
||||
uint32_t vr = VECTOR_INVALID;
|
||||
struct irq_desc *desc;
|
||||
|
||||
spinlock_rflags;
|
||||
|
||||
/* irq should be always available at this time */
|
||||
if (irq > NR_MAX_IRQS || irq < 0)
|
||||
if (irq > NR_MAX_IRQS)
|
||||
return false;
|
||||
|
||||
desc = irq_desc_base + irq;
|
||||
@ -334,7 +334,7 @@ int irq_desc_alloc_vector(int irq, bool lowpri)
|
||||
|
||||
/* FLAT mode, a irq connected to every cpu's same vector */
|
||||
vr = find_available_vector(lowpri);
|
||||
if (vr < 0) {
|
||||
if (vr > NR_MAX_VECTOR) {
|
||||
pr_err("no vector found for irq[%d]", irq);
|
||||
goto OUT;
|
||||
}
|
||||
@ -344,7 +344,7 @@ OUT:
|
||||
return vr;
|
||||
}
|
||||
|
||||
void irq_desc_try_free_vector(int irq)
|
||||
void irq_desc_try_free_vector(uint32_t irq)
|
||||
{
|
||||
struct irq_desc *desc;
|
||||
|
||||
@ -363,7 +363,7 @@ void irq_desc_try_free_vector(int irq)
|
||||
|
||||
}
|
||||
|
||||
int irq_to_vector(int irq)
|
||||
uint32_t irq_to_vector(uint32_t irq)
|
||||
{
|
||||
if (irq < NR_MAX_IRQS)
|
||||
return irq_desc_base[irq].vector;
|
||||
@ -371,12 +371,12 @@ int irq_to_vector(int irq)
|
||||
return VECTOR_INVALID;
|
||||
}
|
||||
|
||||
int dev_to_irq(struct dev_handler_node *node)
|
||||
uint32_t dev_to_irq(struct dev_handler_node *node)
|
||||
{
|
||||
return node->desc->irq;
|
||||
}
|
||||
|
||||
int dev_to_vector(struct dev_handler_node *node)
|
||||
uint32_t dev_to_vector(struct dev_handler_node *node)
|
||||
{
|
||||
return node->desc->vector;
|
||||
}
|
||||
@ -413,7 +413,7 @@ void dispatch_exception(struct intr_excp_ctx *ctx)
|
||||
cpu_dead(cpu_id);
|
||||
}
|
||||
|
||||
void handle_spurious_interrupt(int vector)
|
||||
void handle_spurious_interrupt(uint32_t vector)
|
||||
{
|
||||
send_lapic_eoi();
|
||||
|
||||
@ -428,8 +428,8 @@ void handle_spurious_interrupt(int vector)
|
||||
/* do_IRQ() */
|
||||
void dispatch_interrupt(struct intr_excp_ctx *ctx)
|
||||
{
|
||||
int vr = ctx->vector;
|
||||
int irq = vector_to_irq[vr];
|
||||
uint32_t vr = ctx->vector;
|
||||
uint32_t irq = vector_to_irq[vr];
|
||||
struct irq_desc *desc;
|
||||
|
||||
if (irq == IRQ_INVALID)
|
||||
@ -582,7 +582,7 @@ int quick_handler_nolock(struct irq_desc *desc, __unused void *handler_data)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void update_irq_handler(int irq, irq_handler_t func)
|
||||
void update_irq_handler(uint32_t irq, irq_handler_t func)
|
||||
{
|
||||
struct irq_desc *desc;
|
||||
|
||||
@ -639,7 +639,7 @@ UNLOCK_EXIT:
|
||||
* Allocate IRQ with Vector from 0x20 ~ 0xDF
|
||||
*/
|
||||
struct dev_handler_node*
|
||||
normal_register_handler(int irq,
|
||||
normal_register_handler(uint32_t irq,
|
||||
dev_handler_t func,
|
||||
void *dev_data,
|
||||
bool share,
|
||||
@ -648,7 +648,7 @@ normal_register_handler(int irq,
|
||||
{
|
||||
struct irq_request_info info;
|
||||
|
||||
info.vector = -1;
|
||||
info.vector = VECTOR_INVALID;
|
||||
info.lowpri = lowpri;
|
||||
info.func = func;
|
||||
info.dev_data = dev_data;
|
||||
@ -665,8 +665,8 @@ normal_register_handler(int irq,
|
||||
* times
|
||||
*/
|
||||
struct dev_handler_node*
|
||||
pri_register_handler(int irq,
|
||||
int vector,
|
||||
pri_register_handler(uint32_t irq,
|
||||
uint32_t vector,
|
||||
dev_handler_t func,
|
||||
void *dev_data,
|
||||
const char *name)
|
||||
@ -688,7 +688,8 @@ pri_register_handler(int irq,
|
||||
|
||||
int get_cpu_interrupt_info(char *str, int str_max)
|
||||
{
|
||||
int irq, vector, pcpu_id, len, size = str_max;
|
||||
int pcpu_id;
|
||||
uint32_t irq, vector, len, size = str_max;
|
||||
struct irq_desc *desc;
|
||||
|
||||
len = snprintf(str, size, "\r\nIRQ\tVECTOR");
|
||||
|
||||
@ -20,7 +20,7 @@ static int kick_notification(__unused int irq, __unused void *data)
|
||||
static int request_notification_irq(dev_handler_t func, void *data,
|
||||
const char *name)
|
||||
{
|
||||
int irq = -1; /* system allocate */
|
||||
uint32_t irq = IRQ_INVALID; /* system allocate */
|
||||
struct dev_handler_node *node = NULL;
|
||||
|
||||
if (notification_node != NULL) {
|
||||
|
||||
@ -791,14 +791,14 @@ static int dmar_fault_handler(__unused int irq, void *data)
|
||||
|
||||
static int dmar_setup_interrupt(struct dmar_drhd_rt *dmar_uint)
|
||||
{
|
||||
int vector;
|
||||
uint32_t vector;
|
||||
|
||||
if (dmar_uint->dmar_irq_node) {
|
||||
dev_dbg(ACRN_DBG_IOMMU, "%s: irq already setup", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
dmar_uint->dmar_irq_node = normal_register_handler(-1,
|
||||
dmar_uint->dmar_irq_node = normal_register_handler(IRQ_INVALID,
|
||||
dmar_fault_handler,
|
||||
dmar_uint, true, false,
|
||||
"dmar_fault_event");
|
||||
|
||||
@ -177,7 +177,7 @@ struct vcpu_arch {
|
||||
/* Holds the information needed for IRQ/exception handling. */
|
||||
struct {
|
||||
/* The number of the exception to raise. */
|
||||
int exception;
|
||||
uint32_t exception;
|
||||
|
||||
/* The error number for the exception. */
|
||||
int error;
|
||||
|
||||
@ -37,9 +37,9 @@
|
||||
struct vioapic *vioapic_init(struct vm *vm);
|
||||
void vioapic_cleanup(struct vioapic *vioapic);
|
||||
|
||||
int vioapic_assert_irq(struct vm *vm, int irq);
|
||||
int vioapic_deassert_irq(struct vm *vm, int irq);
|
||||
int vioapic_pulse_irq(struct vm *vm, int irq);
|
||||
int vioapic_assert_irq(struct vm *vm, uint32_t irq);
|
||||
int vioapic_deassert_irq(struct vm *vm, uint32_t irq);
|
||||
int vioapic_pulse_irq(struct vm *vm, uint32_t irq);
|
||||
void vioapic_update_tmr(struct vcpu *vcpu);
|
||||
|
||||
int vioapic_mmio_write(void *vm, uint64_t gpa,
|
||||
@ -48,7 +48,7 @@ int vioapic_mmio_read(void *vm, uint64_t gpa,
|
||||
uint64_t *rval, int size);
|
||||
|
||||
int vioapic_pincount(struct vm *vm);
|
||||
void vioapic_process_eoi(struct vm *vm, int vector);
|
||||
void vioapic_process_eoi(struct vm *vm, uint32_t vector);
|
||||
bool vioapic_get_rte(struct vm *vm, int pin, void *rte);
|
||||
int vioapic_mmio_access_handler(struct vcpu *vcpu, struct mem_io *mmio,
|
||||
void *handler_private_data);
|
||||
|
||||
@ -46,7 +46,7 @@ uint64_t vlapic_get_cr8(struct vlapic *vlapic);
|
||||
* Note that the vector does not automatically transition to the ISR as a
|
||||
* result of calling this function.
|
||||
*/
|
||||
int vlapic_pending_intr(struct vlapic *vlapic, int *vecptr);
|
||||
int vlapic_pending_intr(struct vlapic *vlapic, uint32_t *vecptr);
|
||||
|
||||
/*
|
||||
* Transition 'vector' from IRR to ISR. This function is called with the
|
||||
@ -54,7 +54,7 @@ int vlapic_pending_intr(struct vlapic *vlapic, int *vecptr);
|
||||
* accept this interrupt (i.e. RFLAGS.IF = 1 and no conditions exist that
|
||||
* block interrupt delivery).
|
||||
*/
|
||||
void vlapic_intr_accepted(struct vlapic *vlapic, int vector);
|
||||
void vlapic_intr_accepted(struct vlapic *vlapic, uint32_t vector);
|
||||
|
||||
struct vlapic *vm_lapic_from_vcpuid(struct vm *vm, int vcpu_id);
|
||||
struct vlapic *vm_lapic_from_pcpuid(struct vm *vm, int pcpu_id);
|
||||
@ -69,18 +69,18 @@ int vlapic_mmio_write(struct vcpu *vcpu, uint64_t gpa, uint64_t wval, int size);
|
||||
* Signals to the LAPIC that an interrupt at 'vector' needs to be generated
|
||||
* to the 'cpu', the state is recorded in IRR.
|
||||
*/
|
||||
int vlapic_set_intr(struct vcpu *vcpu, int vector, bool trig);
|
||||
int vlapic_set_intr(struct vcpu *vcpu, uint32_t vector, bool trig);
|
||||
|
||||
#define LAPIC_TRIG_LEVEL true
|
||||
#define LAPIC_TRIG_EDGE false
|
||||
static inline int
|
||||
vlapic_intr_level(struct vcpu *vcpu, int vector)
|
||||
vlapic_intr_level(struct vcpu *vcpu, uint32_t vector)
|
||||
{
|
||||
return vlapic_set_intr(vcpu, vector, LAPIC_TRIG_LEVEL);
|
||||
}
|
||||
|
||||
static inline int
|
||||
vlapic_intr_edge(struct vcpu *vcpu, int vector)
|
||||
vlapic_intr_edge(struct vcpu *vcpu, uint32_t vector)
|
||||
{
|
||||
return vlapic_set_intr(vcpu, vector, LAPIC_TRIG_EDGE);
|
||||
}
|
||||
@ -89,7 +89,7 @@ vlapic_intr_edge(struct vcpu *vcpu, int vector)
|
||||
* Triggers the LAPIC local interrupt (LVT) 'vector' on 'cpu'. 'cpu' can
|
||||
* be set to -1 to trigger the interrupt on all CPUs.
|
||||
*/
|
||||
int vlapic_set_local_intr(struct vm *vm, int cpu, int vector);
|
||||
int vlapic_set_local_intr(struct vm *vm, int cpu, uint32_t vector);
|
||||
|
||||
int vlapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg);
|
||||
|
||||
@ -105,7 +105,7 @@ void vlapic_reset_tmr(struct vlapic *vlapic);
|
||||
* this 'vlapic'.
|
||||
*/
|
||||
void vlapic_set_tmr_one_vec(struct vlapic *vlapic, int delmode,
|
||||
int vector, bool level);
|
||||
uint32_t vector, bool level);
|
||||
|
||||
void
|
||||
vlapic_apicv_batch_set_tmr(struct vlapic *vlapic);
|
||||
|
||||
@ -93,14 +93,14 @@ enum vpic_trigger {
|
||||
void *vpic_init(struct vm *vm);
|
||||
void vpic_cleanup(struct vm *vm);
|
||||
|
||||
int vpic_assert_irq(struct vm *vm, int irq);
|
||||
int vpic_deassert_irq(struct vm *vm, int irq);
|
||||
int vpic_pulse_irq(struct vm *vm, int irq);
|
||||
int vpic_assert_irq(struct vm *vm, uint32_t irq);
|
||||
int vpic_deassert_irq(struct vm *vm, uint32_t irq);
|
||||
int vpic_pulse_irq(struct vm *vm, uint32_t irq);
|
||||
|
||||
void vpic_pending_intr(struct vm *vm, int *vecptr);
|
||||
void vpic_intr_accepted(struct vm *vm, int vector);
|
||||
int vpic_set_irq_trigger(struct vm *vm, int irq, enum vpic_trigger trigger);
|
||||
int vpic_get_irq_trigger(struct vm *vm, int irq, enum vpic_trigger *trigger);
|
||||
void vpic_pending_intr(struct vm *vm, uint32_t *vecptr);
|
||||
void vpic_intr_accepted(struct vm *vm, uint32_t vector);
|
||||
int vpic_set_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger trigger);
|
||||
int vpic_get_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger *trigger);
|
||||
|
||||
struct vm_io_handler *vpic_create_io_handler(int flags, uint32_t port,
|
||||
uint32_t len);
|
||||
|
||||
@ -22,13 +22,13 @@
|
||||
void setup_ioapic_irq(void);
|
||||
int get_ioapic_info(char *str, int str_max_len);
|
||||
|
||||
bool irq_is_gsi(int irq);
|
||||
int irq_gsi_num(void);
|
||||
int irq_to_pin(int irq);
|
||||
int pin_to_irq(int pin);
|
||||
void irq_gsi_mask_unmask(int irq, bool mask);
|
||||
void ioapic_set_rte(int irq, uint64_t rte);
|
||||
void ioapic_get_rte(int irq, uint64_t *rte);
|
||||
bool irq_is_gsi(uint32_t irq);
|
||||
uint32_t irq_gsi_num(void);
|
||||
int irq_to_pin(uint32_t irq);
|
||||
uint32_t pin_to_irq(int pin);
|
||||
void irq_gsi_mask_unmask(uint32_t irq, bool mask);
|
||||
void ioapic_set_rte(uint32_t irq, uint64_t rte);
|
||||
void ioapic_get_rte(uint32_t irq, uint64_t *rte);
|
||||
|
||||
extern uint16_t legacy_irq_to_pin[];
|
||||
extern uint16_t pic_ioapic_pin_map[];
|
||||
|
||||
@ -26,9 +26,9 @@
|
||||
|
||||
#define NR_MAX_VECTOR 0xFF
|
||||
#define VECTOR_INVALID (NR_MAX_VECTOR + 1)
|
||||
#define NR_MAX_IRQS (256+16)
|
||||
#define IRQ_INVALID (NR_MAX_IRQS+1)
|
||||
|
||||
#define NR_MAX_IRQS (256+16)
|
||||
#define DEFAULT_DEST_MODE IOAPIC_RTE_DESTLOG
|
||||
#define DEFAULT_DELIVERY_MODE IOAPIC_RTE_DELLOPRI
|
||||
#define ALL_CPUS_MASK ((1 << phy_cpu_num) - 1)
|
||||
@ -97,15 +97,15 @@ struct intr_excp_ctx {
|
||||
uint64_t ss;
|
||||
};
|
||||
|
||||
int irq_mark_used(int irq);
|
||||
int irq_alloc(void);
|
||||
uint32_t irq_mark_used(uint32_t irq);
|
||||
uint32_t irq_alloc(void);
|
||||
|
||||
int irq_desc_alloc_vector(int irq, bool lowpri);
|
||||
void irq_desc_try_free_vector(int irq);
|
||||
uint32_t irq_desc_alloc_vector(uint32_t irq, bool lowpri);
|
||||
void irq_desc_try_free_vector(uint32_t irq);
|
||||
|
||||
int irq_to_vector(int irq);
|
||||
int dev_to_irq(struct dev_handler_node *node);
|
||||
int dev_to_vector(struct dev_handler_node *node);
|
||||
uint32_t irq_to_vector(uint32_t irq);
|
||||
uint32_t dev_to_irq(struct dev_handler_node *node);
|
||||
uint32_t dev_to_vector(struct dev_handler_node *node);
|
||||
|
||||
int handle_level_interrupt_common(struct irq_desc *desc, void *handler_data);
|
||||
int common_handler_edge(struct irq_desc *desc, void *handler_data);
|
||||
@ -113,21 +113,21 @@ int common_dev_handler_level(struct irq_desc *desc, void *handler_data);
|
||||
int quick_handler_nolock(struct irq_desc *desc, void *handler_data);
|
||||
|
||||
typedef int (*irq_handler_t)(struct irq_desc*, void*);
|
||||
void update_irq_handler(int irq, irq_handler_t func);
|
||||
void update_irq_handler(uint32_t irq, irq_handler_t func);
|
||||
|
||||
int init_default_irqs(unsigned int cpu);
|
||||
|
||||
void dispatch_interrupt(struct intr_excp_ctx *ctx);
|
||||
|
||||
struct dev_handler_node*
|
||||
pri_register_handler(int irq,
|
||||
int vector,
|
||||
pri_register_handler(uint32_t irq,
|
||||
uint32_t vector,
|
||||
dev_handler_t func,
|
||||
void *dev_data,
|
||||
const char *name);
|
||||
|
||||
struct dev_handler_node*
|
||||
normal_register_handler(int irq,
|
||||
normal_register_handler(uint32_t irq,
|
||||
dev_handler_t func,
|
||||
void *dev_data,
|
||||
bool share,
|
||||
@ -139,7 +139,7 @@ int get_cpu_interrupt_info(char *str, int str_max);
|
||||
|
||||
void setup_notification(void);
|
||||
|
||||
typedef void (*spurious_handler_t)(int);
|
||||
typedef void (*spurious_handler_t)(uint32_t vector);
|
||||
extern spurious_handler_t spurious_handler;
|
||||
|
||||
/*
|
||||
@ -162,7 +162,7 @@ int vcpu_inject_nmi(struct vcpu *vcpu);
|
||||
int vcpu_inject_gp(struct vcpu *vcpu, uint32_t err_code);
|
||||
int vcpu_inject_pf(struct vcpu *vcpu, uint64_t addr, uint32_t err_code);
|
||||
int vcpu_make_request(struct vcpu *vcpu, int eventid);
|
||||
int vcpu_queue_exception(struct vcpu *vcpu, int32_t vector, uint32_t err_code);
|
||||
int vcpu_queue_exception(struct vcpu *vcpu, uint32_t vector, uint32_t err_code);
|
||||
|
||||
int exception_vmexit_handler(struct vcpu *vcpu);
|
||||
int interrupt_window_vmexit_handler(struct vcpu *vcpu);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user