irq: convert irq/vector numbers to unsigned

Currently irq and vector numbers are used inconsistently.

    * Sometimes vector or irq ids is used in bit operations, indicating
      that they should be unsigned (which is required by MISRA C).

    * At the same time we use -1 to indicate an unknown irq (in
      common_register_handler()) or unavailable irq (in
      alloc_irq()). Also (irq < 0) or (vector < 0) are used for error
      checking. These indicate that irq or vector ids should be signed.

This patch converts irq and vector numbers to unsigned 32-bit integers, and
replace the previous -1 with IRQ_INVALID or VECTOR_INVALID. The branch
conditions are updated accordingly.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

hypervisor/include/arch/x86/guest/vcpu.h

@@ -177,7 +177,7 @@ struct vcpu_arch {
 	/* Holds the information needed for IRQ/exception handling. */
 	struct {
 		/* The number of the exception to raise. */
-		int exception;
+		uint32_t exception;
 
 		/* The error number for the exception. */
 		int error;

hypervisor/include/arch/x86/guest/vioapic.h

@@ -37,9 +37,9 @@
 struct vioapic *vioapic_init(struct vm *vm);
 void	vioapic_cleanup(struct vioapic *vioapic);
 
-int	vioapic_assert_irq(struct vm *vm, int irq);
-int	vioapic_deassert_irq(struct vm *vm, int irq);
-int	vioapic_pulse_irq(struct vm *vm, int irq);
+int	vioapic_assert_irq(struct vm *vm, uint32_t irq);
+int	vioapic_deassert_irq(struct vm *vm, uint32_t irq);
+int	vioapic_pulse_irq(struct vm *vm, uint32_t irq);
 void	vioapic_update_tmr(struct vcpu *vcpu);
 
 int	vioapic_mmio_write(void *vm, uint64_t gpa,
@@ -48,7 +48,7 @@ int	vioapic_mmio_read(void *vm, uint64_t gpa,
 	    uint64_t *rval, int size);
 
 int	vioapic_pincount(struct vm *vm);
-void	vioapic_process_eoi(struct vm *vm, int vector);
+void	vioapic_process_eoi(struct vm *vm, uint32_t vector);
 bool	vioapic_get_rte(struct vm *vm, int pin, void *rte);
 int	vioapic_mmio_access_handler(struct vcpu *vcpu, struct mem_io *mmio,
 		void *handler_private_data);

hypervisor/include/arch/x86/guest/vlapic.h

@@ -46,7 +46,7 @@ uint64_t vlapic_get_cr8(struct vlapic *vlapic);
  * Note that the vector does not automatically transition to the ISR as a
  * result of calling this function.
  */
-int vlapic_pending_intr(struct vlapic *vlapic, int *vecptr);
+int vlapic_pending_intr(struct vlapic *vlapic, uint32_t *vecptr);
 
 /*
  * Transition 'vector' from IRR to ISR. This function is called with the
@@ -54,7 +54,7 @@ int vlapic_pending_intr(struct vlapic *vlapic, int *vecptr);
  * accept this interrupt (i.e. RFLAGS.IF = 1 and no conditions exist that
  * block interrupt delivery).
  */
-void vlapic_intr_accepted(struct vlapic *vlapic, int vector);
+void vlapic_intr_accepted(struct vlapic *vlapic, uint32_t vector);
 
 struct vlapic *vm_lapic_from_vcpuid(struct vm *vm, int vcpu_id);
 struct vlapic *vm_lapic_from_pcpuid(struct vm *vm, int pcpu_id);
@@ -69,18 +69,18 @@ int vlapic_mmio_write(struct vcpu *vcpu, uint64_t gpa, uint64_t wval, int size);
  * Signals to the LAPIC that an interrupt at 'vector' needs to be generated
  * to the 'cpu', the state is recorded in IRR.
  */
-int vlapic_set_intr(struct vcpu *vcpu, int vector, bool trig);
+int vlapic_set_intr(struct vcpu *vcpu, uint32_t vector, bool trig);
 
 #define	LAPIC_TRIG_LEVEL	true
 #define	LAPIC_TRIG_EDGE		false
 static inline int
-vlapic_intr_level(struct vcpu *vcpu, int vector)
+vlapic_intr_level(struct vcpu *vcpu, uint32_t vector)
 {
 	return vlapic_set_intr(vcpu, vector, LAPIC_TRIG_LEVEL);
 }
 
 static inline int
-vlapic_intr_edge(struct vcpu *vcpu, int vector)
+vlapic_intr_edge(struct vcpu *vcpu, uint32_t vector)
 {
 	return vlapic_set_intr(vcpu, vector, LAPIC_TRIG_EDGE);
 }
@@ -89,7 +89,7 @@ vlapic_intr_edge(struct vcpu *vcpu, int vector)
  * Triggers the LAPIC local interrupt (LVT) 'vector' on 'cpu'.  'cpu' can
  * be set to -1 to trigger the interrupt on all CPUs.
  */
-int vlapic_set_local_intr(struct vm *vm, int cpu, int vector);
+int vlapic_set_local_intr(struct vm *vm, int cpu, uint32_t vector);
 
 int vlapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg);
 
@@ -105,7 +105,7 @@ void vlapic_reset_tmr(struct vlapic *vlapic);
  * this 'vlapic'.
  */
 void vlapic_set_tmr_one_vec(struct vlapic *vlapic, int delmode,
-		int vector, bool level);
+		uint32_t vector, bool level);
 
 void
 vlapic_apicv_batch_set_tmr(struct vlapic *vlapic);

hypervisor/include/arch/x86/guest/vpic.h

@@ -93,14 +93,14 @@ enum vpic_trigger {
 void *vpic_init(struct vm *vm);
 void vpic_cleanup(struct vm *vm);
 
-int vpic_assert_irq(struct vm *vm, int irq);
-int vpic_deassert_irq(struct vm *vm, int irq);
-int vpic_pulse_irq(struct vm *vm, int irq);
+int vpic_assert_irq(struct vm *vm, uint32_t irq);
+int vpic_deassert_irq(struct vm *vm, uint32_t irq);
+int vpic_pulse_irq(struct vm *vm, uint32_t irq);
 
-void vpic_pending_intr(struct vm *vm, int *vecptr);
-void vpic_intr_accepted(struct vm *vm, int vector);
-int vpic_set_irq_trigger(struct vm *vm, int irq, enum vpic_trigger trigger);
-int vpic_get_irq_trigger(struct vm *vm, int irq, enum vpic_trigger *trigger);
+void vpic_pending_intr(struct vm *vm, uint32_t *vecptr);
+void vpic_intr_accepted(struct vm *vm, uint32_t vector);
+int vpic_set_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger trigger);
+int vpic_get_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger *trigger);
 
 struct vm_io_handler *vpic_create_io_handler(int flags, uint32_t port,
 	uint32_t len);

hypervisor/include/arch/x86/ioapic.h

@@ -22,13 +22,13 @@
 void setup_ioapic_irq(void);
 int get_ioapic_info(char *str, int str_max_len);
 
-bool irq_is_gsi(int irq);
-int irq_gsi_num(void);
-int irq_to_pin(int irq);
-int pin_to_irq(int pin);
-void irq_gsi_mask_unmask(int irq, bool mask);
-void ioapic_set_rte(int irq, uint64_t rte);
-void ioapic_get_rte(int irq, uint64_t *rte);
+bool irq_is_gsi(uint32_t irq);
+uint32_t irq_gsi_num(void);
+int irq_to_pin(uint32_t irq);
+uint32_t pin_to_irq(int pin);
+void irq_gsi_mask_unmask(uint32_t irq, bool mask);
+void ioapic_set_rte(uint32_t irq, uint64_t rte);
+void ioapic_get_rte(uint32_t irq, uint64_t *rte);
 
 extern uint16_t legacy_irq_to_pin[];
 extern uint16_t pic_ioapic_pin_map[];

hypervisor/include/arch/x86/irq.h

@@ -26,9 +26,9 @@
 
 #define NR_MAX_VECTOR		0xFF
 #define VECTOR_INVALID		(NR_MAX_VECTOR + 1)
+#define NR_MAX_IRQS		(256+16)
 #define IRQ_INVALID		(NR_MAX_IRQS+1)
 
-#define NR_MAX_IRQS (256+16)
 #define DEFAULT_DEST_MODE	IOAPIC_RTE_DESTLOG
 #define DEFAULT_DELIVERY_MODE	IOAPIC_RTE_DELLOPRI
 #define ALL_CPUS_MASK		((1 << phy_cpu_num) - 1)
@@ -97,15 +97,15 @@ struct intr_excp_ctx {
 	uint64_t ss;
 };
 
-int irq_mark_used(int irq);
-int irq_alloc(void);
+uint32_t irq_mark_used(uint32_t irq);
+uint32_t irq_alloc(void);
 
-int irq_desc_alloc_vector(int irq, bool lowpri);
-void irq_desc_try_free_vector(int irq);
+uint32_t irq_desc_alloc_vector(uint32_t irq, bool lowpri);
+void irq_desc_try_free_vector(uint32_t irq);
 
-int irq_to_vector(int irq);
-int dev_to_irq(struct dev_handler_node *node);
-int dev_to_vector(struct dev_handler_node *node);
+uint32_t irq_to_vector(uint32_t irq);
+uint32_t dev_to_irq(struct dev_handler_node *node);
+uint32_t dev_to_vector(struct dev_handler_node *node);
 
 int handle_level_interrupt_common(struct irq_desc *desc, void *handler_data);
 int common_handler_edge(struct irq_desc *desc, void *handler_data);
@@ -113,21 +113,21 @@ int common_dev_handler_level(struct irq_desc *desc, void *handler_data);
 int quick_handler_nolock(struct irq_desc *desc, void *handler_data);
 
 typedef int (*irq_handler_t)(struct irq_desc*, void*);
-void update_irq_handler(int irq, irq_handler_t func);
+void update_irq_handler(uint32_t irq, irq_handler_t func);
 
 int init_default_irqs(unsigned int cpu);
 
 void dispatch_interrupt(struct intr_excp_ctx *ctx);
 
 struct dev_handler_node*
-pri_register_handler(int irq,
-		int vector,
+pri_register_handler(uint32_t irq,
+		uint32_t vector,
 		dev_handler_t func,
 		void *dev_data,
 		const char *name);
 
 struct dev_handler_node*
-normal_register_handler(int irq,
+normal_register_handler(uint32_t irq,
 		dev_handler_t func,
 		void *dev_data,
 		bool share,
@@ -139,7 +139,7 @@ int get_cpu_interrupt_info(char *str, int str_max);
 
 void setup_notification(void);
 
-typedef void (*spurious_handler_t)(int);
+typedef void (*spurious_handler_t)(uint32_t vector);
 extern spurious_handler_t spurious_handler;
 
 /*
@@ -162,7 +162,7 @@ int vcpu_inject_nmi(struct vcpu *vcpu);
 int vcpu_inject_gp(struct vcpu *vcpu, uint32_t err_code);
 int vcpu_inject_pf(struct vcpu *vcpu, uint64_t addr, uint32_t err_code);
 int vcpu_make_request(struct vcpu *vcpu, int eventid);
-int vcpu_queue_exception(struct vcpu *vcpu, int32_t vector, uint32_t err_code);
+int vcpu_queue_exception(struct vcpu *vcpu, uint32_t vector, uint32_t err_code);
 
 int exception_vmexit_handler(struct vcpu *vcpu);
 int interrupt_window_vmexit_handler(struct vcpu *vcpu);