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DM: change high RAM start address to 4GB for post-launched VM

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ACRN didn't support dynamic memory allocation. SO it would reserve
a big page pool and use the GPA as index to get a page to do EPT
mapping. In order to save memory, we put high MMIO windows to [4G, 5G].
AFter we support dynamic page allocation for EPT mapping, we move
high MMIO windows to where it used to ([256G, 512G]) for 39 bits physical
address), we could move high memory to where is used to too ([4G, 4G +
size]).

Tracked-On: #5913
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
This commit is contained in:
Tao Yuhong 2021-03-16 07:09:26 -04:00 committed by wenlingz
parent 5ceae97ab4
commit 8ed1d8aa5e
3 changed files with 6 additions and 3 deletions
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4
devicemodel/core/sw_load_common.c
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@ -58,7 +58,7 @@ static char bootargs[BOOT_ARG_LEN];
* 3: gpu_rsvd_bot - gpu_rsvd_top (reserved) 0x4004000 * 3: gpu_rsvd_bot - gpu_rsvd_top (reserved) 0x4004000
* 4: lowmem part2 - 0x80000000 (reserved) 0x0 * 4: lowmem part2 - 0x80000000 (reserved) 0x0
* 5: 0xE0000000 - 0x100000000 MCFG, MMIO 512MB * 5: 0xE0000000 - 0x100000000 MCFG, MMIO 512MB
* 6: 0x140000000 - highmem RAM highmem - 5GB * 6: HIGHRAM_START_ADDR - mmio64 start RAM ctx->highmem
* *
* FIXME: Do we need to reserve DSM and OPREGION for GVTD here. * FIXME: Do we need to reserve DSM and OPREGION for GVTD here.
*/ */
@ -106,7 +106,7 @@ const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
}, },
{ /* 5GB to highmem */ { /* 5GB to highmem */
.baseaddr = PCI_EMUL_MEMLIMIT64, .baseaddr = HIGHRAM_START_ADDR,
.length = 0x0, .length = 0x0,
.type = E820_TYPE_RESERVED .type = E820_TYPE_RESERVED
}, },

3
devicemodel/core/vmmapi.c
View File

@ -46,6 +46,7 @@
#include "dm.h" #include "dm.h"
#include "pci_core.h" #include "pci_core.h"
#include "log.h" #include "log.h"
#include "sw_load.h"
#define MAP_NOCORE 0 #define MAP_NOCORE 0
#define MAP_ALIGNED_SUPER 0 #define MAP_ALIGNED_SUPER 0
@ -229,7 +230,7 @@ vm_create(const char *name, uint64_t req_buf, int *vcpu_num)
ctx->gvt_enabled = false; ctx->gvt_enabled = false;
ctx->fd = devfd; ctx->fd = devfd;
ctx->lowmem_limit = PCI_EMUL_MEMBASE32; ctx->lowmem_limit = PCI_EMUL_MEMBASE32;
ctx->highmem_gpa_base = PCI_EMUL_MEMLIMIT64; ctx->highmem_gpa_base = HIGHRAM_START_ADDR;
ctx->name = (char *)(ctx + 1); ctx->name = (char *)(ctx + 1);
strncpy(ctx->name, name, strnlen(name, PATH_MAX) + 1); strncpy(ctx->name, name, strnlen(name, PATH_MAX) + 1);

2
devicemodel/include/sw_load.h
View File

@ -43,6 +43,8 @@
#define LOWRAM_E820_ENTRY 1 #define LOWRAM_E820_ENTRY 1
#define HIGHRAM_E820_ENTRY 6 #define HIGHRAM_E820_ENTRY 6
#define HIGHRAM_START_ADDR 0x100000000UL /* 4GB */
/* Defines a single entry in an E820 memory map. */ /* Defines a single entry in an E820 memory map. */
struct e820_entry { struct e820_entry {
/** The base address of the memory range. */ /** The base address of the memory range. */