hv: pgtable: move pgtable definition to pgtable.h

This patch moves pgtable definition to pgtable.h and include the proper
header file for page module.

Tracked-On: #5830
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

hypervisor/arch/x86/mmu.c

@@ -29,7 +29,6 @@
 
 #include <types.h>
 #include <atomic.h>
-#include <page.h>
 #include <pgtable.h>
 #include <cpu_caps.h>
 #include <mmu.h>

hypervisor/arch/x86/page.c

@@ -4,15 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #include <types.h>
-#include <rtl.h>
+#include <bits.h>
-#include <cpufeatures.h>
-#include <pgtable.h>
 #include <page.h>
-#include <mmu.h>
-#include <trusty.h>
-#include <vtd.h>
-#include <security.h>
-#include <vm.h>
 #include <logmsg.h>
 
 

hypervisor/include/arch/x86/guest/ept.h

@@ -17,6 +17,9 @@ typedef void (*pge_handler)(uint64_t *pgentry, uint64_t size);
  */
 #define INVALID_HPA	(0x1UL << 52U)
 #define INVALID_GPA	(0x1UL << 52U)
+
+struct acrn_vm;
+
 /* External Interfaces */
 /**
  * @brief Check if the GPA range is guest valid GPA or not

hypervisor/include/arch/x86/guest/vm.h

@@ -15,6 +15,7 @@
 
 #include <bits.h>
 #include <spinlock.h>
+#include <pgtable.h>
 #include <vcpu.h>
 #include <vioapic.h>
 #include <vpic.h>

hypervisor/include/arch/x86/page.h

@@ -8,7 +8,6 @@
 #define PAGE_H
 
 #include <spinlock.h>
-#include <board_info.h>
 
 #define PAGE_SHIFT	12U
 #define PAGE_SIZE	(1U << PAGE_SHIFT)
@@ -29,30 +28,6 @@
 #define PT_PAGE_NUM(size)	(((size) + PDE_SIZE - 1UL) >> PDE_SHIFT)
 
 
-/**
- * @brief Page tables level in IA32 paging mode
- */
-enum _page_table_level {
-        /**
-         * @brief The PML4 level in the page tables
-         */
-	IA32E_PML4 = 0,
-        /**
-         * @brief The Page-Directory-Pointer-Table level in the page tables
-         */
-	IA32E_PDPT = 1,
-        /**
-         * @brief The Page-Directory level in the page tables
-         */
-	IA32E_PD = 2,
-        /**
-         * @brief The Page-Table level in the page tables
-         */
-	IA32E_PT = 3,
-};
-
-struct acrn_vm;
-
 struct page {
 	uint8_t contents[PAGE_SIZE];
 } __aligned(PAGE_SIZE);
@@ -67,16 +42,6 @@ struct page_pool {
 	struct page *dummy_page;
 };
 
-struct pgtable {
-	uint64_t default_access_right;
-	struct page_pool *pool;
-	bool (*large_page_support)(enum _page_table_level level, uint64_t prot);
-	uint64_t (*pgentry_present)(uint64_t pte);
-	void (*clflush_pagewalk)(const void *p);
-	void (*tweak_exe_right)(uint64_t *entry);
-	void (*recover_exe_right)(uint64_t *entry);
-};
-
 struct page *alloc_page(struct page_pool *pool);
 void free_page(struct page_pool *pool, struct page *page);
 #endif /* PAGE_H */

hypervisor/include/arch/x86/pgtable.h

@@ -136,6 +136,39 @@
 #define PML4E_PFN_MASK		0x0000FFFFFFFFF000UL
 #define PDPTE_PFN_MASK		0x0000FFFFFFFFF000UL
 #define PDE_PFN_MASK		0x0000FFFFFFFFF000UL
+
+/**
+ * @brief Page tables level in IA32 paging mode
+ */
+enum _page_table_level {
+        /**
+         * @brief The PML4 level in the page tables
+         */
+	IA32E_PML4 = 0,
+        /**
+         * @brief The Page-Directory-Pointer-Table level in the page tables
+         */
+	IA32E_PDPT = 1,
+        /**
+         * @brief The Page-Directory level in the page tables
+         */
+	IA32E_PD = 2,
+        /**
+         * @brief The Page-Table level in the page tables
+         */
+	IA32E_PT = 3,
+};
+
+struct pgtable {
+	uint64_t default_access_right;
+	struct page_pool *pool;
+	bool (*large_page_support)(enum _page_table_level level, uint64_t prot);
+	uint64_t (*pgentry_present)(uint64_t pte);
+	void (*clflush_pagewalk)(const void *p);
+	void (*tweak_exe_right)(uint64_t *entry);
+	void (*recover_exe_right)(uint64_t *entry);
+};
+
 /**
  * @brief Address space translation
  *