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HV:CPU: Narrow integer conversion
There are some narrow integer conversion violations in the HV reported by static analysis tools. The narrow integer conversions are resolved by following methods: * Explicit type conversion as needed; * Update suffix of constant value as 'U' as needed. cked-on: ccm0001001-247033 Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
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@ -114,7 +114,7 @@ static void get_cpu_capabilities(void)
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family = (eax >> 8U) & 0xffU;
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if (family == 0xFU)
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family += (eax >> 20U) & 0xffU;
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boot_cpu_data.x86 = family;
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boot_cpu_data.x86 = (uint8_t)family;
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model = (eax >> 4U) & 0xfU;
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if (family >= 0x06U)
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@ -651,7 +651,7 @@ static void update_trampoline_code_refs(uint64_t dest_pa)
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val = dest_pa + (uint64_t)trampoline_fixup_target;
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ptr = HPA2HVA(dest_pa + (uint64_t)trampoline_fixup_cs);
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*(uint16_t *)(ptr) = (uint16_t)(val >> 4) & 0xFFFFU;
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*(uint16_t *)(ptr) = (uint16_t)((val >> 4) & 0xFFFFU);
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ptr = HPA2HVA(dest_pa + (uint64_t)trampoline_fixup_ip);
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*(uint16_t *)(ptr) = (uint16_t)(val & 0xfU);
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@ -673,7 +673,7 @@ static void update_trampoline_code_refs(uint64_t dest_pa)
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/* update trampoline jump pointer with relocated offset */
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ptr = HPA2HVA(dest_pa + (uint64_t)trampoline_start64_fixup);
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*(uint32_t *)ptr += dest_pa;
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*(uint32_t *)ptr += (uint32_t)dest_pa;
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}
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static uint64_t prepare_trampoline(void)
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@ -690,7 +690,7 @@ static uint64_t prepare_trampoline(void)
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pr_dbg("trampoline code: %llx size %x", dest_pa, size);
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/* Copy segment for AP initialization code below 1MB */
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(void)memcpy_s(HPA2HVA(dest_pa), size, _ld_trampoline_load, size);
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(void)memcpy_s(HPA2HVA(dest_pa), (size_t)size, _ld_trampoline_load, (size_t)size);
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update_trampoline_code_refs(dest_pa);
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trampoline_start16_paddr = dest_pa;
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@ -15,73 +15,73 @@
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#define CPUID_H_
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/* CPUID bit definitions */
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#define CPUID_ECX_SSE3 (1UL<<0)
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#define CPUID_ECX_PCLMUL (1UL<<1)
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#define CPUID_ECX_DTES64 (1UL<<2)
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#define CPUID_ECX_MONITOR (1UL<<3)
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#define CPUID_ECX_DS_CPL (1UL<<4)
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#define CPUID_ECX_VMX (1UL<<5)
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#define CPUID_ECX_SMX (1UL<<6)
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#define CPUID_ECX_EST (1UL<<7)
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#define CPUID_ECX_TM2 (1UL<<8)
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#define CPUID_ECX_SSSE3 (1UL<<9)
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#define CPUID_ECX_CID (1UL<<10)
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#define CPUID_ECX_FMA (1UL<<12)
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#define CPUID_ECX_CX16 (1UL<<13)
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#define CPUID_ECX_ETPRD (1UL<<14)
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#define CPUID_ECX_PDCM (1UL<<15)
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#define CPUID_ECX_DCA (1UL<<18)
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#define CPUID_ECX_SSE4_1 (1UL<<19)
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#define CPUID_ECX_SSE4_2 (1UL<<20)
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#define CPUID_ECX_x2APIC (1UL<<21)
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#define CPUID_ECX_MOVBE (1UL<<22)
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#define CPUID_ECX_POPCNT (1UL<<23)
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#define CPUID_ECX_AES (1UL<<25)
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#define CPUID_ECX_XSAVE (1UL<<26)
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#define CPUID_ECX_OSXSAVE (1UL<<27)
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#define CPUID_ECX_AVX (1UL<<28)
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#define CPUID_EDX_FPU (1UL<<0)
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#define CPUID_EDX_VME (1UL<<1)
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#define CPUID_EDX_DE (1UL<<2)
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#define CPUID_EDX_PSE (1UL<<3)
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#define CPUID_EDX_TSC (1UL<<4)
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#define CPUID_EDX_MSR (1UL<<5)
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#define CPUID_EDX_PAE (1UL<<6)
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#define CPUID_EDX_MCE (1UL<<7)
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#define CPUID_EDX_CX8 (1UL<<8)
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#define CPUID_EDX_APIC (1UL<<9)
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#define CPUID_EDX_SEP (1UL<<11)
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#define CPUID_EDX_MTRR (1UL<<12)
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#define CPUID_EDX_PGE (1UL<<13)
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#define CPUID_EDX_MCA (1UL<<14)
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#define CPUID_EDX_CMOV (1UL<<15)
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#define CPUID_EDX_PAT (1UL<<16)
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#define CPUID_EDX_PSE36 (1UL<<17)
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#define CPUID_EDX_PSN (1UL<<18)
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#define CPUID_EDX_CLF (1UL<<19)
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#define CPUID_EDX_DTES (1UL<<21)
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#define CPUID_EDX_ACPI (1UL<<22)
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#define CPUID_EDX_MMX (1UL<<23)
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#define CPUID_EDX_FXSR (1UL<<24)
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#define CPUID_EDX_SSE (1UL<<25)
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#define CPUID_EDX_SSE2 (1UL<<26)
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#define CPUID_EDX_SS (1UL<<27)
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#define CPUID_EDX_HTT (1UL<<28)
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#define CPUID_EDX_TM1 (1UL<<29)
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#define CPUID_EDX_IA64 (1UL<<30)
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#define CPUID_EDX_PBE (1UL<<31)
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#define CPUID_ECX_SSE3 (1U<<0)
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#define CPUID_ECX_PCLMUL (1U<<1)
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#define CPUID_ECX_DTES64 (1U<<2)
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#define CPUID_ECX_MONITOR (1U<<3)
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#define CPUID_ECX_DS_CPL (1U<<4)
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#define CPUID_ECX_VMX (1U<<5)
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#define CPUID_ECX_SMX (1U<<6)
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#define CPUID_ECX_EST (1U<<7)
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#define CPUID_ECX_TM2 (1U<<8)
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#define CPUID_ECX_SSSE3 (1U<<9)
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#define CPUID_ECX_CID (1U<<10)
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#define CPUID_ECX_FMA (1U<<12)
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#define CPUID_ECX_CX16 (1U<<13)
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#define CPUID_ECX_ETPRD (1U<<14)
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#define CPUID_ECX_PDCM (1U<<15)
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#define CPUID_ECX_DCA (1U<<18)
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#define CPUID_ECX_SSE4_1 (1U<<19)
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#define CPUID_ECX_SSE4_2 (1U<<20)
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#define CPUID_ECX_x2APIC (1U<<21)
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#define CPUID_ECX_MOVBE (1U<<22)
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#define CPUID_ECX_POPCNT (1U<<23)
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#define CPUID_ECX_AES (1U<<25)
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#define CPUID_ECX_XSAVE (1U<<26)
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#define CPUID_ECX_OSXSAVE (1U<<27)
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#define CPUID_ECX_AVX (1U<<28)
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#define CPUID_EDX_FPU (1U<<0)
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#define CPUID_EDX_VME (1U<<1)
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#define CPUID_EDX_DE (1U<<2)
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#define CPUID_EDX_PSE (1U<<3)
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#define CPUID_EDX_TSC (1U<<4)
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#define CPUID_EDX_MSR (1U<<5)
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#define CPUID_EDX_PAE (1U<<6)
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#define CPUID_EDX_MCE (1U<<7)
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#define CPUID_EDX_CX8 (1U<<8)
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#define CPUID_EDX_APIC (1U<<9)
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#define CPUID_EDX_SEP (1U<<11)
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#define CPUID_EDX_MTRR (1U<<12)
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#define CPUID_EDX_PGE (1U<<13)
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#define CPUID_EDX_MCA (1U<<14)
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#define CPUID_EDX_CMOV (1U<<15)
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#define CPUID_EDX_PAT (1U<<16)
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#define CPUID_EDX_PSE36 (1U<<17)
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#define CPUID_EDX_PSN (1U<<18)
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#define CPUID_EDX_CLF (1U<<19)
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#define CPUID_EDX_DTES (1U<<21)
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#define CPUID_EDX_ACPI (1U<<22)
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#define CPUID_EDX_MMX (1U<<23)
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#define CPUID_EDX_FXSR (1U<<24)
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#define CPUID_EDX_SSE (1U<<25)
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#define CPUID_EDX_SSE2 (1U<<26)
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#define CPUID_EDX_SS (1U<<27)
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#define CPUID_EDX_HTT (1U<<28)
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#define CPUID_EDX_TM1 (1U<<29)
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#define CPUID_EDX_IA64 (1U<<30)
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#define CPUID_EDX_PBE (1U<<31)
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/* CPUID.07H:EBX.TSC_ADJUST*/
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#define CPUID_EBX_TSC_ADJ (1UL<<1)
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#define CPUID_EBX_TSC_ADJ (1U<<1)
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/* CPUID.07H:EDX.IBRS_IBPB*/
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#define CPUID_EDX_IBRS_IBPB (1UL<<26)
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#define CPUID_EDX_IBRS_IBPB (1U<<26)
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/* CPUID.07H:EDX.STIBP*/
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#define CPUID_EDX_STIBP (1UL<<27)
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#define CPUID_EDX_STIBP (1U<<27)
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/* CPUID.80000001H:EDX.Page1GB*/
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#define CPUID_EDX_PAGE1GB (1UL<<26)
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#define CPUID_EDX_PAGE1GB (1U<<26)
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/* CPUID.07H:EBX.INVPCID*/
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#define CPUID_EBX_INVPCID (1UL<<10)
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#define CPUID_EBX_INVPCID (1U<<10)
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/* CPUID.01H:ECX.PCID*/
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#define CPUID_ECX_PCID (1UL<<17)
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#define CPUID_ECX_PCID (1U<<17)
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/* CPUID source operands */
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#define CPUID_VENDORSTRING 0
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