acrn-config: Reorg config tool folder

Remove vm_configs folder and move all the XML files and generic code example into config_tools/data

Tracked-On: #5644
Signed-off-by: Xie, nanlin <nanlin.xie@intel.com>

CODEOWNERS

@@ -16,13 +16,12 @@ Makefile                                 @terryzouhao
 /hypervisor/                             @anthonyzxu @dongyaozu
 /devicemodel/                            @anthonyzxu @ywan170
 /doc/                                    @dbkinder @deb-intel @NanlinXie
-/misc/tools/acrn-crashlog/               @chengangc @dizhang417 
-/misc/tools/acrnlog/                     @ywan170 @liuyuan-GitHub
-/misc/tools/acrntrace/                   @ywan170 @liuyuan-GitHub
-/misc/acrn-manager/                      @ywan170 @liuyuan-GitHub
-/misc/acrnbridge/                        @ywan170 @liuyuan-GitHub
-/misc/acrn-config/                       @terryzouhao
+/misc/debug_tools/acrn_crashlog/         @chengangc @dizhang417
+/misc/debug_tools/acrn_log/              @ywan170 @shuox
+/misc/debug_tools/acrn_trace/            @ywan170 @shuox
+/misc/services/acrn_manager/             @ywan170 @shuox
+/misc/services/acrn_bridge/              @ywan170 @shuox
+/misc/config_tools/                      @terryzouhao
 /misc/Makefile                           @terryzouhao
-/misc/efi-stub/                          @terryzouhao
 
 *.rst                                    @dbkinder @deb-intel @NanlinXie

Makefile

@@ -68,12 +68,12 @@ O ?= build
 ROOT_OUT := $(shell mkdir -p $(O);cd $(O);pwd)
 HV_OUT := $(ROOT_OUT)/hypervisor
 DM_OUT := $(ROOT_OUT)/devicemodel
-TOOLS_OUT := $(ROOT_OUT)/misc/tools
+TOOLS_OUT := $(ROOT_OUT)/misc/debug_tools
 DOC_OUT := $(ROOT_OUT)/doc
 BUILD_VERSION ?=
 BUILD_TAG ?=
 HV_CFG_LOG = $(HV_OUT)/cfg.log
-VM_CONFIGS_DIR = $(T)/misc/vm_configs
+VM_CONFIGS_DIR = $(T)/misc/config_tools
 
 export TOOLS_OUT BOARD SCENARIO RELEASE
 

devicemodel/samples

@@ -1 +1 @@
-../misc/vm_configs/sample_launch_scripts/
+../misc/config_tools/data/sample_launch_scripts/

doc/develop.rst

@@ -19,10 +19,10 @@ Configuration and Tools
    user-guides/kernel-parameters
    user-guides/acrn-shell
    user-guides/acrn-dm-parameters
-   misc/tools/acrn-crashlog/README
+   misc/debug_tools/acrn_crashlog/README
    misc/packaging/README
-   misc/tools/**
-   misc/acrn-manager/**
+   misc/debug_tools/**
+   misc/services/acrn_manager/**
 
 Service VM Tutorials
 ********************

hypervisor/Makefile

@@ -382,7 +382,7 @@ pre_build: $(HV_CONFIG_H) $(HV_CONFIG_TIMESTAMP)
 	$(MAKE) -C $(PRE_BUILD_DIR) BOARD=$(BOARD) SCENARIO=$(SCENARIO) TARGET_DIR=$(HV_CONFIG_DIR)
 	@$(HV_OBJDIR)/hv_prebuild_check.out
 	@echo "generate the binary of ACPI tables for pre-launched VMs ..."
-	python3 ../misc/acrn-config/acpi_gen/bin_gen.py --board $(BOARD) --scenario $(SCENARIO) --asl $(HV_CONFIG_DIR) --out $(HV_OBJDIR)/acpi
+	python3 ../misc/config_tools/acpi_gen/bin_gen.py --board $(BOARD) --scenario $(SCENARIO) --asl $(HV_CONFIG_DIR) --out $(HV_OBJDIR)/acpi
 
 .PHONY: header
 header: $(VERSION) $(HV_CONFIG_H)

hypervisor/scripts/genconf.sh

@@ -16,7 +16,7 @@ apply_patch () {
     fi
 }
 
-tool_dir=${base_dir}/../misc/acrn-config
+tool_dir=${base_dir}/../misc/config_tools
 diffconfig_list=${out}/.diffconfig
 
 python3 ${tool_dir}/board_config/board_cfg_gen.py --board ${board_xml} --scenario ${scenario_xml} --out ${out} &&

hypervisor/scripts/makefile/cfg_update.mk

@@ -45,13 +45,13 @@ update_config:
 ifeq ($(CONFIG_XML_ENABLED),true)
 	@if [ ! -f $(UPDATE_RESULT) ]; then \
 		mkdir -p $(dir $(UPDATE_RESULT));\
-		python3 ../misc/acrn-config/board_config/board_cfg_gen.py --board $(BOARD_FILE) --scenario $(SCENARIO_FILE) --out $(TARGET_DIR) > $(UPDATE_RESULT);\
+		python3 ../misc/config_tools/board_config/board_cfg_gen.py --board $(BOARD_FILE) --scenario $(SCENARIO_FILE) --out $(TARGET_DIR) > $(UPDATE_RESULT);\
 		cat $(UPDATE_RESULT);\
 		if [ "`sed -n /successfully/p $(UPDATE_RESULT)`" = "" ]; then rm -f $(UPDATE_RESULT); exit 1;	fi;\
 		if [ "$(TARGET_DIR)" = "" ]; then \
-			python3 ../misc/acrn-config/scenario_config/scenario_cfg_gen.py --board $(BOARD_FILE) --scenario $(SCENARIO_FILE) > $(UPDATE_RESULT);\
+			python3 ../misc/config_tools/scenario_config/scenario_cfg_gen.py --board $(BOARD_FILE) --scenario $(SCENARIO_FILE) > $(UPDATE_RESULT);\
 		else \
-			python3 ../misc/acrn-config/scenario_config/scenario_cfg_gen.py --board $(BOARD_FILE) --scenario $(SCENARIO_FILE) --out $(abspath $(TARGET_DIR)) > $(UPDATE_RESULT);\
+			python3 ../misc/config_tools/scenario_config/scenario_cfg_gen.py --board $(BOARD_FILE) --scenario $(SCENARIO_FILE) --out $(abspath $(TARGET_DIR)) > $(UPDATE_RESULT);\
 		fi;\
 		cat $(UPDATE_RESULT);\
 		if [ "`sed -n /successfully/p $(UPDATE_RESULT)`" = "" ]; then rm -f $(UPDATE_RESULT); exit 1;	fi;\

hypervisor/scripts/makefile/config.mk

@@ -50,13 +50,13 @@ endef
 #
 #   * The <symbol>_FILE (i.e. either BOARD_FILE or SCENARIO_FILE) will always hold the path to an existing XML file that
 #     defines the effective board/scenario. If only a BOARD/SCENARIO name is given, a predefined configuration under
-#     misc/acrn-config/xmls will be used.
+#     misc/config_tools/data/$BOARD will be used.
 #
 define determine_config =
 ifneq ($($(1)),)
   ifneq ($(realpath $($(1))),)
     override $(1)_FILE := $($(1))
-    override $(1) := $$(shell xmllint --xpath 'string(/acrn-config/@$(shell echo $(1) | tr A-Z a-z))' $$($(1)_FILE))
+    override $(1) := $$(shell xmllint --xpath 'string(/config_tools/@$(shell echo $(1) | tr A-Z a-z))' $$($(1)_FILE))
   else
     override $(1)_FILE := $(HV_PREDEFINED_$(1)_DIR)/$$($(1)).xml
     ifeq ($$(realpath $$($(1)_FILE)),)
@@ -113,9 +113,9 @@ endef
 HV_BOARD_XML := $(HV_OBJDIR)/.board.xml
 HV_SCENARIO_XML := $(HV_OBJDIR)/.scenario.xml
 HV_UNIFIED_XML_IN := $(BASEDIR)/scripts/makefile/unified.xml.in
-HV_PREDEFINED_BOARD_DIR := $(realpath $(BASEDIR)/../misc/acrn-config/xmls/board-xmls)
-HV_PREDEFINED_SCENARIO_DIR = $(realpath $(BASEDIR)/../misc/acrn-config/xmls/config-xmls)/$(BOARD)
-HV_CONFIG_TOOL_DIR := $(realpath $(BASEDIR)/../misc/acrn-config)
+HV_PREDEFINED_BOARD_DIR := $(realpath $(BASEDIR)/../misc/config_tools/data)/$(BOARD)
+HV_PREDEFINED_SCENARIO_DIR = $(realpath $(BASEDIR)/../misc/config_tools/data)/$(BOARD)
+HV_CONFIG_TOOL_DIR := $(realpath $(BASEDIR)/../misc/config_tools)
 HV_CONFIG_XFORM_DIR := $(HV_CONFIG_TOOL_DIR)/xforms
 
 # Paths to the outputs:

hypervisor/scripts/makefile/kconfig.mk

@@ -18,7 +18,7 @@ HV_DEFCONFIG := defconfig
 HV_CONFIG_H := include/config.h
 HV_CONFIG_MK := include/config.mk
 
-KCONFIG_DIR := $(BASEDIR)/../misc/acrn-config/kconfig
+KCONFIG_DIR := $(BASEDIR)/../misc/config_tools/kconfig
 
 # Backward-compatibility for RELEASE=(0|1)
 ifdef RELEASE

misc/acrn-config/xmls

@@ -1 +0,0 @@
-../vm_configs/xmls/

misc/config_tools/acpi_gen/acpi_const.py

@@ -10,8 +10,8 @@ import os, sys
 sys.path.append(os.path.join(os.path.dirname(os.path.abspath(__file__)), '..', 'library'))
 import common
 
-VM_CONFIGS_PATH = os.path.join(common.SOURCE_ROOT_DIR, 'misc', 'vm_configs')
-TEMPLATE_ACPI_PATH = os.path.join(VM_CONFIGS_PATH, 'acpi', 'template')
+VM_CONFIGS_PATH = os.path.join(common.SOURCE_ROOT_DIR, 'misc', 'config_tools')
+TEMPLATE_ACPI_PATH = os.path.join(VM_CONFIGS_PATH, 'acpi_template', 'template')
 
 ACPI_TABLE_LIST = [('rsdp.asl', 'rsdp.aml'), ('xsdt.asl', 'xsdt.aml'), ('facp.asl', 'facp.aml'),
                    ('mcfg.asl', 'mcfg.aml'), ('apic.asl', 'apic.aml'), ('tpm2.asl', 'tpm2.aml'),

misc/config_tools/acpi_gen/bin_gen.py

@@ -202,9 +202,7 @@ if __name__ == '__main__':
                                      description="the tool to generate ACPI binary for Pre-launched VMs.")
     parser.add_argument("--board", required=True, help="the board type.")
     parser.add_argument("--scenario", required=True, help="the scenario name.")
-    parser.add_argument("--asl", default=None, help="the input folder to store the ACPI ASL code. "
-                                                    "If not specified, the path for the ASL code is"
-                                                    "misc/vm_configs/scenarios/[scenario]/[board]/")
+    parser.add_argument("--asl", default=None, help="the input folder to store the ACPI ASL code. ")
     parser.add_argument("--out", default=None, help="the output folder to store the ACPI binary code. "
                                                     "If not specified, the path for the binary code is"
                                                     "build/acpi/")

misc/config_tools/board_config/board_cfg_gen.py

@@ -17,7 +17,7 @@ import common
 import vbar_base_h
 
 ACRN_PATH = common.SOURCE_ROOT_DIR
-ACRN_CONFIG_DEF = ACRN_PATH + "misc/vm_configs/"
+ACRN_CONFIG_DEF = ACRN_PATH + "misc/config_tools/data/"
 
 ACRN_DEFAULT_ACPI = ACRN_PATH + "hypervisor/include/arch/x86/default_acpi_info.h"
 GEN_FILE = ["pci_devices.h", "board.c", "platform_acpi_info.h", "misc_cfg.h",

misc/config_tools/data/generic/generic.xml

@@ -0,0 +1,425 @@
+<acrn-config board="ehl-crb-b">
+	<BIOS_INFO>
+	BIOS Information
+	Vendor: Intel Corporation
+	Version: EHLSFWI1.R00.2224.A00.2005281500
+	Release Date: 05/28/2020
+	</BIOS_INFO>
+
+	<BASE_BOARD_INFO>
+	Base Board Information
+	Manufacturer: Intel Corporation
+	Product Name: ElkhartLake LPDDR4x T3 CRB
+	Version: 2
+	</BASE_BOARD_INFO>
+
+	<PCI_DEVICE>
+	00:00.0 Host bridge: Intel Corporation Device 4532
+	00:02.0 VGA compatible controller: Intel Corporation Device 4571
+	Region 0: Memory at 82000000 (64-bit, non-prefetchable) [size=16M]
+	Region 2: Memory at 70000000 (64-bit, prefetchable) [size=256M]
+	00:08.0 System peripheral: Intel Corporation Device 4511
+	Region 0: Memory at 834e4000 (64-bit, non-prefetchable) [disabled] [size=4K]
+	00:10.0 Serial bus controller [0c80]: Intel Corporation Device 4b44
+	Region 0: Memory at 83441000 (64-bit, non-prefetchable) [virtual] [size=4K]
+	00:10.1 Serial bus controller [0c80]: Intel Corporation Device 4b45
+	Region 0: Memory at 83444000 (64-bit, non-prefetchable) [virtual] [size=4K]
+	00:13.0 Serial bus controller [0c80]: Intel Corporation Device 4b84
+	Region 0: Memory at 834d8000 (64-bit, non-prefetchable) [disabled] [size=8K]
+	00:13.4 Communication controller: Intel Corporation Device 4b88
+	Region 0: Memory at 84600000 (64-bit, non-prefetchable) [size=16K]
+	00:13.5 Communication controller: Intel Corporation Device 4b89
+	Region 0: Memory at 845fc000 (64-bit, non-prefetchable) [size=16K]
+	00:14.0 USB controller: Intel Corporation Device 4b7d
+	Region 0: Memory at 834c0000 (64-bit, non-prefetchable) [size=64K]
+	00:14.2 RAM memory: Intel Corporation Device 4b7f
+	Region 0: Memory at 834d0000 (64-bit, non-prefetchable) [disabled] [size=16K]
+	Region 2: Memory at 834e7000 (64-bit, non-prefetchable) [disabled] [size=4K]
+	00:15.0 Serial bus controller [0c80]: Intel Corporation Device 4b78
+	Region 0: Memory at 83445000 (64-bit, non-prefetchable) [virtual] [size=4K]
+	00:15.2 Serial bus controller [0c80]: Intel Corporation Device 4b7a
+	Region 0: Memory at 83446000 (64-bit, non-prefetchable) [virtual] [size=4K]
+	00:15.3 Serial bus controller [0c80]: Intel Corporation Device 4b7b
+	Region 0: Memory at 83447000 (64-bit, non-prefetchable) [virtual] [size=4K]
+	00:16.0 Communication controller: Intel Corporation Device 4b70
+	Region 0: Memory at 834eb000 (64-bit, non-prefetchable) [size=4K]
+	00:17.0 SATA controller: Intel Corporation Device 4b63
+	Region 0: Memory at 834e2000 (32-bit, non-prefetchable) [size=8K]
+	Region 1: Memory at 834f6000 (32-bit, non-prefetchable) [size=256]
+	Region 5: Memory at 834f5000 (32-bit, non-prefetchable) [size=2K]
+	00:19.0 Serial bus controller [0c80]: Intel Corporation Device 4b4b
+	Region 0: Memory at 83448000 (64-bit, non-prefetchable) [virtual] [size=4K]
+	00:19.2 Communication controller: Intel Corporation Device 4b4d
+	Region 0: Memory at 83449000 (64-bit, non-prefetchable) [size=4K]
+	00:1a.0 SD Host controller: Intel Corporation Device 4b47
+	Region 0: Memory at 834ee000 (64-bit, non-prefetchable) [size=4K]
+	00:1a.1 SD Host controller: Intel Corporation Device 4b48
+	Region 0: Memory at 834ef000 (64-bit, non-prefetchable) [size=4K]
+	00:1a.3 Non-VGA unclassified device: Intel Corporation Device 4b4a
+	Region 0: Memory at 83400000 (64-bit, non-prefetchable) [disabled] [size=256K]
+	00:1b.0 Serial bus controller [0c80]: Intel Corporation Device 4bb9
+	Region 0: Memory at 834da000 (64-bit, non-prefetchable) [size=8K]
+	00:1b.1 Serial bus controller [0c80]: Intel Corporation Device 4bba
+	Region 0: Memory at 834dc000 (64-bit, non-prefetchable) [size=8K]
+	00:1b.6 Serial bus controller [0c80]: Intel Corporation Device 4bbf
+	Region 0: Memory at 834de000 (64-bit, non-prefetchable) [size=8K]
+	00:1c.0 PCI bridge: Intel Corporation Device 4b38
+	00:1d.0 System peripheral: Intel Corporation Device 4bb3
+	Region 0: Memory at 83000000 (64-bit, non-prefetchable) [disabled] [size=2M]
+	00:1d.1 Ethernet controller: Intel Corporation Device 4ba0
+	Region 0: Memory at 83500000 (64-bit, non-prefetchable) [disabled] [size=256K]
+	00:1d.2 Ethernet controller: Intel Corporation Device 4bb0
+	Region 0: Memory at 83480000 (64-bit, non-prefetchable) [disabled] [size=256K]
+	00:1e.0 Communication controller: Intel Corporation Device 4b28
+	Region 0: Memory at 8344a000 (64-bit, non-prefetchable) [size=4K]
+	00:1e.1 Communication controller: Intel Corporation Device 4b29
+	Region 0: Memory at 8344b000 (64-bit, non-prefetchable) [size=4K]
+	00:1e.4 Ethernet controller: Intel Corporation Device 4b32
+	Region 0: Memory at 83442000 (64-bit, non-prefetchable) [disabled] [size=8K]
+	Region 2: Memory at 834f2000 (64-bit, non-prefetchable) [disabled] [size=4K]
+	00:1f.0 ISA bridge: Intel Corporation Device 4b00
+	00:1f.3 Multimedia audio controller: Intel Corporation Device 4b58
+	Region 0: Memory at 834d4000 (64-bit, non-prefetchable) [size=16K]
+	Region 4: Memory at 83200000 (64-bit, non-prefetchable) [size=1M]
+	00:1f.4 SMBus: Intel Corporation Device 4b23
+	Region 0: Memory at 834f3000 (64-bit, non-prefetchable) [size=256]
+	00:1f.5 Serial bus controller [0c80]: Intel Corporation Device 4b24
+	Region 0: Memory at 8344c000 (32-bit, non-prefetchable) [size=4K]
+	Region 1: Memory at 80000000 (32-bit, non-prefetchable) [size=32M]
+	01:00.0 Non-Volatile memory controller: Silicon Motion, Inc. Device 2263 (rev 03)
+	Region 0: Memory at 83300000 (64-bit, non-prefetchable) [size=16K]
+	</PCI_DEVICE>
+
+	<PCI_VID_PID>
+	00:00.0 0600: 8086:4532
+	00:02.0 0300: 8086:4571
+	00:08.0 0880: 8086:4511
+	00:10.0 0c80: 8086:4b44
+	00:10.1 0c80: 8086:4b45
+	00:13.0 0c80: 8086:4b84
+	00:13.4 0780: 8086:4b88
+	00:13.5 0780: 8086:4b89
+	00:14.0 0c03: 8086:4b7d
+	00:14.2 0500: 8086:4b7f
+	00:15.0 0c80: 8086:4b78
+	00:15.2 0c80: 8086:4b7a
+	00:15.3 0c80: 8086:4b7b
+	00:16.0 0780: 8086:4b70
+	00:17.0 0106: 8086:4b63
+	00:19.0 0c80: 8086:4b4b
+	00:19.2 0780: 8086:4b4d
+	00:1a.0 0805: 8086:4b47
+	00:1a.1 0805: 8086:4b48
+	00:1a.3 0000: 8086:4b4a
+	00:1b.0 0c80: 8086:4bb9
+	00:1b.1 0c80: 8086:4bba
+	00:1b.6 0c80: 8086:4bbf
+	00:1c.0 0604: 8086:4b38
+	00:1d.0 0880: 8086:4bb3
+	00:1d.1 0200: 8086:4ba0
+	00:1d.2 0200: 8086:4bb0
+	00:1e.0 0780: 8086:4b28
+	00:1e.1 0780: 8086:4b29
+	00:1e.4 0200: 8086:4b32
+	00:1f.0 0601: 8086:4b00
+	00:1f.3 0401: 8086:4b58
+	00:1f.4 0c05: 8086:4b23
+	00:1f.5 0c80: 8086:4b24
+	01:00.0 0108: 126f:2263 (rev 03)
+	</PCI_VID_PID>
+
+	<WAKE_VECTOR_INFO>
+	#define WAKE_VECTOR_32          0x66BB000CUL
+	#define WAKE_VECTOR_64          0x66BB0018UL
+	</WAKE_VECTOR_INFO>
+
+	<RESET_REGISTER_INFO>
+	#define RESET_REGISTER_ADDRESS  0xCF9UL
+	#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
+	#define RESET_REGISTER_VALUE    0x6U
+	</RESET_REGISTER_INFO>
+
+	<PM_INFO>
+	#define PM1A_EVT_SPACE_ID       SPACE_SYSTEM_IO
+	#define PM1A_EVT_BIT_WIDTH      0x20U
+	#define PM1A_EVT_BIT_OFFSET     0x0U
+	#define PM1A_EVT_ADDRESS        0x1800UL
+	#define PM1A_EVT_ACCESS_SIZE    0x2U
+	#define PM1B_EVT_SPACE_ID       SPACE_SYSTEM_IO
+	#define PM1B_EVT_BIT_WIDTH      0x0U
+	#define PM1B_EVT_BIT_OFFSET     0x0U
+	#define PM1B_EVT_ADDRESS        0x0UL
+	#define PM1B_EVT_ACCESS_SIZE    0x2U
+	#define PM1A_CNT_SPACE_ID       SPACE_SYSTEM_IO
+	#define PM1A_CNT_BIT_WIDTH      0x10U
+	#define PM1A_CNT_BIT_OFFSET     0x0U
+	#define PM1A_CNT_ADDRESS        0x1804UL
+	#define PM1A_CNT_ACCESS_SIZE    0x2U
+	#define PM1B_CNT_SPACE_ID       SPACE_SYSTEM_IO
+	#define PM1B_CNT_BIT_WIDTH      0x0U
+	#define PM1B_CNT_BIT_OFFSET     0x0U
+	#define PM1B_CNT_ADDRESS        0x0UL
+	#define PM1B_CNT_ACCESS_SIZE    0x2U
+	</PM_INFO>
+
+	<S3_INFO>
+	#define S3_PKG_VAL_PM1A         0x5U
+	#define S3_PKG_VAL_PM1B         0U
+	#define S3_PKG_RESERVED         0x0U
+	</S3_INFO>
+
+	<S5_INFO>
+	#define S5_PKG_VAL_PM1A         0x7U
+	#define S5_PKG_VAL_PM1B         0U
+	#define S5_PKG_RESERVED         0x0U
+	</S5_INFO>
+
+	<DRHD_INFO>
+	#define DRHD_COUNT              3U
+
+	#define DRHD0_DEV_CNT           0x1U
+	#define DRHD0_SEGMENT           0x0U
+	#define DRHD0_FLAGS             0x0U
+	#define DRHD0_REG_BASE          0xFED90000UL
+	#define DRHD0_IGNORE            true
+	#define DRHD0_DEVSCOPE0_TYPE    0x1U
+	#define DRHD0_DEVSCOPE0_ID      0x0U
+	#define DRHD0_DEVSCOPE0_BUS     0x0U
+	#define DRHD0_DEVSCOPE0_PATH    0x10U
+
+	#define DRHD1_DEV_CNT           0x2U
+	#define DRHD1_SEGMENT           0x0U
+	#define DRHD1_FLAGS             0x1U
+	#define DRHD1_REG_BASE          0xFED91000UL
+	#define DRHD1_IGNORE            false
+	#define DRHD1_DEVSCOPE0_TYPE    0x3U
+	#define DRHD1_DEVSCOPE0_ID      0x2U
+	#define DRHD1_DEVSCOPE0_BUS     0x0U
+	#define DRHD1_DEVSCOPE0_PATH    0xf7U
+	#define DRHD1_DEVSCOPE1_TYPE    0x4U
+	#define DRHD1_DEVSCOPE1_ID      0x0U
+	#define DRHD1_DEVSCOPE1_BUS     0x0U
+	#define DRHD1_DEVSCOPE1_PATH    0xf6U
+
+	#define DRHD2_DEV_CNT           0x3U
+	#define DRHD2_SEGMENT           0x0U
+	#define DRHD2_FLAGS             0x0U
+	#define DRHD2_REG_BASE          0x00UL
+	#define DRHD2_IGNORE            false
+	#define DRHD2_DEVSCOPE0_TYPE    0x5U
+	#define DRHD2_DEVSCOPE0_ID      0x3U
+	#define DRHD2_DEVSCOPE0_BUS     0x0U
+	#define DRHD2_DEVSCOPE0_PATH    0xebU
+	#define DRHD2_DEVSCOPE1_TYPE    0x5U
+	#define DRHD2_DEVSCOPE1_ID      0x4U
+	#define DRHD2_DEVSCOPE1_BUS     0x0U
+	#define DRHD2_DEVSCOPE1_PATH    0xecU
+	#define DRHD2_DEVSCOPE2_TYPE    0x5U
+	#define DRHD2_DEVSCOPE2_ID      0x5U
+	#define DRHD2_DEVSCOPE2_BUS     0x0U
+	#define DRHD2_DEVSCOPE2_PATH    0xedU
+
+	</DRHD_INFO>
+
+	<CPU_BRAND>
+	"Genuine Intel(R) CPU 0000 @ 1.50GHz"
+	</CPU_BRAND>
+
+	<CX_INFO>
+	{{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x01U, 0x00U},	/* C1 */
+	{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1816UL}, 0x02U, 0xFDU, 0x00U},	/* C2 */
+	{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1819UL}, 0x03U, 0x418U, 0x00U},	/* C3 */
+	</CX_INFO>
+
+	<PX_INFO>
+	{0x5DDUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL},	/* P0 */
+	{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL},	/* P1 */
+	</PX_INFO>
+
+	<MMCFG_BASE_INFO>
+	/* PCI mmcfg base of MCFG */
+	#define DEFAULT_PCI_MMCFG_BASE   0xc0000000UL
+	</MMCFG_BASE_INFO>
+
+	<CLOS_INFO>
+	rdt resources supported: L2
+	rdt resource clos max: 16
+	rdt resource mask max: '0xfff'
+	</CLOS_INFO>
+
+	<IOMEM_INFO>
+	00000000-00000fff : Reserved
+	00001000-0009efff : System RAM
+	0009f000-000fffff : Reserved
+	  000a0000-000bffff : PCI Bus 0000:00
+	  000f0000-000fffff : System ROM
+	00100000-3fffffff : System RAM
+	40000000-403fffff : Reserved
+	40400000-6146bfff : System RAM
+	6146c000-6146cfff : Reserved
+	6146d000-6485cfff : System RAM
+	6485d000-648b9fff : Unknown E820 type
+	648ba000-66b8bfff : Reserved
+	  65043000-65052fff : pnp 00:03
+	66b8c000-66be5fff : ACPI Non-volatile Storage
+	66be6000-66c4efff : ACPI Tables
+	66c4f000-66c4ffff : System RAM
+	66c50000-6fffffff : Reserved
+	  6c000000-6fffffff : Graphics Stolen Memory
+	70000000-bfffffff : PCI Bus 0000:00
+	  70000000-7fffffff : 0000:00:02.0
+	  80000000-81ffffff : 0000:00:1f.5
+	  82000000-82ffffff : 0000:00:02.0
+	  83000000-831fffff : 0000:00:1d.0
+	  83200000-832fffff : 0000:00:1f.3
+	    83200000-832fffff : ICH HD audio
+	  83300000-833fffff : PCI Bus 0000:01
+	    83300000-83303fff : 0000:01:00.0
+	      83300000-83303fff : nvme
+	  83400000-8343ffff : 0000:00:1a.3
+	  83440200-83440203 : INTC1033:01
+	  83440204-83440207 : INTC1033:01
+	  83441000-83441fff : 0000:00:10.0
+	    83441000-834411ff : lpss_dev
+	      83441000-834411ff : i2c_designware.0
+	    83441200-834412ff : lpss_priv
+	  83442000-83443fff : 0000:00:1e.4
+	  83444000-83444fff : 0000:00:10.1
+	    83444000-834441ff : lpss_dev
+	      83444000-834441ff : i2c_designware.1
+	    83444200-834442ff : lpss_priv
+	  83445000-83445fff : 0000:00:15.0
+	    83445000-834451ff : lpss_dev
+	      83445000-834451ff : i2c_designware.2
+	    83445200-834452ff : lpss_priv
+	    83445800-83445fff : idma64.2
+	      83445800-83445fff : idma64.2
+	  83446000-83446fff : 0000:00:15.2
+	    83446000-834461ff : lpss_dev
+	      83446000-834461ff : i2c_designware.3
+	    83446200-834462ff : lpss_priv
+	    83446800-83446fff : idma64.3
+	      83446800-83446fff : idma64.3
+	  83447000-83447fff : 0000:00:15.3
+	    83447000-834471ff : lpss_dev
+	      83447000-834471ff : i2c_designware.4
+	    83447200-834472ff : lpss_priv
+	    83447800-83447fff : idma64.4
+	      83447800-83447fff : idma64.4
+	  83448000-83448fff : 0000:00:19.0
+	    83448000-834481ff : lpss_dev
+	      83448000-834481ff : i2c_designware.5
+	    83448200-834482ff : lpss_priv
+	    83448800-83448fff : idma64.5
+	      83448800-83448fff : idma64.5
+	  83449000-83449fff : 0000:00:19.2
+	    83449000-834491ff : lpss_dev
+	      83449000-8344901f : serial
+	    83449200-834492ff : lpss_priv
+	    83449800-83449fff : idma64.6
+	      83449800-83449fff : idma64.6
+	  8344a000-8344afff : 0000:00:1e.0
+	    8344a000-8344a1ff : lpss_dev
+	      8344a000-8344a01f : serial
+	    8344a200-8344a2ff : lpss_priv
+	    8344a800-8344afff : idma64.7
+	      8344a800-8344afff : idma64.7
+	  8344b000-8344bfff : 0000:00:1e.1
+	    8344b000-8344b1ff : lpss_dev
+	      8344b000-8344b01f : serial
+	    8344b200-8344b2ff : lpss_priv
+	    8344b800-8344bfff : idma64.8
+	      8344b800-8344bfff : idma64.8
+	  8344c000-8344cfff : 0000:00:1f.5
+	  83480000-834bffff : 0000:00:1d.2
+	  834c0000-834cffff : 0000:00:14.0
+	    834c0000-834cffff : xhci-hcd
+	  834d0000-834d3fff : 0000:00:14.2
+	  834d4000-834d7fff : 0000:00:1f.3
+	    834d4000-834d7fff : ICH HD audio
+	  834d8000-834d9fff : 0000:00:13.0
+	  834da000-834dbfff : 0000:00:1b.0
+	    834da000-834dbfff : 0000:00:1b.0
+	  834dc000-834ddfff : 0000:00:1b.1
+	    834dc000-834ddfff : 0000:00:1b.1
+	  834de000-834dffff : 0000:00:1b.6
+	    834de000-834dffff : 0000:00:1b.6
+	  834e0200-834e0203 : INTC1033:00
+	  834e0204-834e0207 : INTC1033:00
+	  834e2000-834e3fff : 0000:00:17.0
+	    834e2000-834e3fff : ahci
+	  834e4000-834e4fff : 0000:00:08.0
+	  834e7000-834e7fff : 0000:00:14.2
+	  834eb000-834ebfff : 0000:00:16.0
+	  834ee000-834eefff : 0000:00:1a.0
+	    834ee000-834eefff : mmc0
+	  834ef000-834effff : 0000:00:1a.1
+	  834f2000-834f2fff : 0000:00:1e.4
+	  834f3000-834f30ff : 0000:00:1f.4
+	  834f5000-834f57ff : 0000:00:17.0
+	    834f5000-834f57ff : ahci
+	  834f6000-834f60ff : 0000:00:17.0
+	    834f6000-834f60ff : ahci
+	  83500000-8353ffff : 0000:00:1d.1
+	c0000000-cfffffff : PCI MMCONFIG 0000 [bus 00-ff]
+	  c0000000-cfffffff : pnp 00:03
+	fd000000-fd68ffff : pnp 00:04
+	fd690000-fd69ffff : INTC1020:00
+	fd6a0000-fd6affff : INTC1020:00
+	fd6b0000-fd6bffff : INTC1020:00
+	fd6c0000-fd6cffff : INTC1020:00
+	fd6d0000-fd6dffff : INTC1020:00
+	fd6e0000-fd6effff : INTC1020:00
+	fd6f0000-fdffffff : pnp 00:04
+	fe000000-fe01ffff : pnp 00:04
+	fe032000-fe032fff : pnp 00:02
+	fe033000-fe033fff : pnp 00:02
+	fe200000-fe7fffff : pnp 00:04
+	fec00000-fec003ff : IOAPIC 0
+	fec80000-fecfffff : pnp 00:03
+	fed00000-fed003ff : HPET 0
+	  fed00000-fed003ff : PNP0103:00
+	fed20000-fed7ffff : Reserved
+	  fed20000-fed7ffff : pnp 00:03
+	fed90000-fed93fff : pnp 00:03
+	feda0000-feda0fff : pnp 00:03
+	feda1000-feda1fff : pnp 00:03
+	fee00000-feefffff : pnp 00:03
+	  fee00000-fee00fff : Local APIC
+	ff300000-ffffffff : Reserved
+	100000000-28fffffff : System RAM
+	  178800000-1798010f0 : Kernel code
+	  1798010f1-179f79dff : Kernel data
+	  17a147000-17a3fffff : Kernel bss
+	</IOMEM_INFO>
+
+	<BLOCK_DEVICE_INFO>
+	/dev/nvme0n1p3: TYPE="ext4"
+	/dev/sda3: TYPE="ext4"
+	/dev/mmcblk0p3: TYPE="ext4"
+	</BLOCK_DEVICE_INFO>
+
+	<TTYS_INFO>
+	seri:/dev/ttyS0 type:mmio base:0x83449000 irq:33 bdf:"00:19.2"
+	seri:/dev/ttyS1 type:mmio base:0x8344A000 irq:16 bdf:"00:1e.0"
+	seri:/dev/ttyS2 type:mmio base:0x8344B000 irq:17 bdf:"00:1e.1"
+	seri:/dev/ttyS3 type:mmio base:0xfe042000 irq:3
+	</TTYS_INFO>
+
+	<AVAILABLE_IRQ_INFO>
+	4, 5, 6, 7, 10, 11, 12, 13, 14, 15
+	</AVAILABLE_IRQ_INFO>
+
+	<TOTAL_MEM_INFO>
+	7960904 kB
+	</TOTAL_MEM_INFO>
+
+	<CPU_PROCESSOR_INFO>
+	0, 1, 2, 3
+	</CPU_PROCESSOR_INFO>
+
+	<MAX_MSIX_TABLE_NUM>
+	16
+	</MAX_MSIX_TABLE_NUM>
+
+</acrn-config>

misc/config_tools/data/generic/hybrid.xml

@@ -0,0 +1,225 @@
+<?xml version='1.0' encoding='utf-8'?>
+<acrn-config board="generic" scenario="hybrid">
+    <hv>
+        <DEBUG_OPTIONS desc="Debug options for ACRN hypervisor, only valid on debug version">
+            <RELEASE desc="Release build. 'y' for Release, 'n' for Debug.">n</RELEASE>
+            <SERIAL_CONSOLE desc="The serial device which is used for hypervisor debug, only valid on Debug version.">/dev/ttyS0</SERIAL_CONSOLE>
+            <MEM_LOGLEVEL desc="Default loglevel in memory">5</MEM_LOGLEVEL>
+            <NPK_LOGLEVEL desc="Default loglevel for the hypervisor NPK log">5</NPK_LOGLEVEL>
+            <CONSOLE_LOGLEVEL desc="Default loglevel on the serial console">3</CONSOLE_LOGLEVEL>
+            <LOG_DESTINATION desc="Bitmap of consoles where logs are printed.">7</LOG_DESTINATION>
+            <LOG_BUF_SIZE desc="Capacity of logbuf for each physical cpu.">0x40000</LOG_BUF_SIZE>
+        </DEBUG_OPTIONS>
+        <FEATURES>
+            <RELOC desc="Enable hypervisor relocation">y</RELOC>
+            <SCHEDULER desc="The CPU scheduler to be used by the hypervisor.">SCHED_BVT</SCHEDULER>
+            <MULTIBOOT2 desc="Support boot ACRN from multiboot2 protocol.">y</MULTIBOOT2>
+            <RDT desc="Intel RDT (Resource Director Technology).">
+                <RDT_ENABLED desc="Enable RDT">n</RDT_ENABLED>
+                <CDP_ENABLED desc="CDP (Code and Data Prioritization). CDP is an extension of CAT.">n</CDP_ENABLED>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+            </RDT>
+            <HYPERV_ENABLED desc="Enable Hyper-V enlightenment">y</HYPERV_ENABLED>
+            <IOMMU_ENFORCE_SNP desc="IOMMU enforce snoop behavior of DMA operation.">n</IOMMU_ENFORCE_SNP>
+            <ACPI_PARSE_ENABLED desc="Enable ACPI runtime parsing.">y</ACPI_PARSE_ENABLED>
+            <L1D_VMENTRY_ENABLED desc="Enable L1 cache flush before VM entry.">n</L1D_VMENTRY_ENABLED>
+            <MCE_ON_PSC_DISABLED desc="Force to disable software workaround for Machine Check Error on Page Size Change.">n</MCE_ON_PSC_DISABLED>
+            <IVSHMEM desc="IVSHMEM configuration">
+                <IVSHMEM_ENABLED desc="Enable Share Memory between VMs by IVSHMEM.">n</IVSHMEM_ENABLED>
+                <IVSHMEM_REGION desc="the shared memory region name (starting with hv:/, size (in MB), and IDs of all VMs (separated by a colon) sharing this region, for example hv:/sharename,2,0:2"></IVSHMEM_REGION>
+            </IVSHMEM>
+        </FEATURES>
+        <MEMORY>
+            <STACK_SIZE desc="Capacity of one stack, in bytes.">0x2000</STACK_SIZE>
+            <HV_RAM_SIZE desc="Size of the RAM region used by the hypervisor" />
+            <HV_RAM_START desc="2M-aligned Start physical address of the RAM region used by the hypervisor." />
+            <LOW_RAM_SIZE desc="Size of the low RAM region">0x00010000</LOW_RAM_SIZE>
+            <UOS_RAM_SIZE desc="Size of the User OS (UOS) RAM.">0x200000000</UOS_RAM_SIZE>
+            <SOS_RAM_SIZE desc="Size of the Service OS (SOS) RAM.">0x400000000</SOS_RAM_SIZE>
+            <PLATFORM_RAM_SIZE desc="Size of the physical platform RAM">0x400000000</PLATFORM_RAM_SIZE>
+        </MEMORY>
+        <CAPACITIES desc="Capacity limits for static assigned data struct or maximum supported resouce">
+            <IOMMU_BUS_NUM desc="Highest PCI bus ID used during IOMMU initialization.">0x100</IOMMU_BUS_NUM>
+            <MAX_IR_ENTRIES desc="Maximum number of Interrupt Remapping Entries.">256</MAX_IR_ENTRIES>
+            <MAX_IOAPIC_NUM desc="Maximum number of IO-APICs.">1</MAX_IOAPIC_NUM>
+            <MAX_PCI_DEV_NUM desc="Maximum number of PCI devices.">96</MAX_PCI_DEV_NUM>
+            <MAX_IOAPIC_LINES desc="Maximum number of interrupt lines per IOAPIC.">120</MAX_IOAPIC_LINES>
+            <MAX_PT_IRQ_ENTRIES desc="Maximum number of interrupt source for PT devices.">256</MAX_PT_IRQ_ENTRIES>
+            <MAX_MSIX_TABLE_NUM desc="Maximum number of MSI-X tables per device. Please leave it blank if not sure.">64</MAX_MSIX_TABLE_NUM>
+            <MAX_EMULATED_MMIO desc="Maximum number of emulated MMIO regions.">16</MAX_EMULATED_MMIO>
+        </CAPACITIES>
+        <MISC_CFG>
+            <GPU_SBDF desc="Segment, Bus, Device, and function of the GPU.">0x00000010</GPU_SBDF>
+        </MISC_CFG>
+    </hv>
+    <vm id="0">
+        <vm_type desc="Specify the VM type" readonly="true">SAFETY_VM</vm_type>
+        <name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN PRE-LAUNCHED VM0</name>
+        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+            <guest_flag>0</guest_flag>
+        </guest_flags>
+        <cpu_affinity desc="List of pCPU that this VM's vCPUs are pinned to.">
+            <pcpu_id>3</pcpu_id>
+        </cpu_affinity>
+        <pt_intx desc="pt intx mapping.">
+        </pt_intx>
+        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+            <vcpu_clos>0</vcpu_clos>
+        </clos>
+        <epc_section configurable="0" desc="epc section">
+            <base desc="SGX EPC section base, must be page aligned">0</base>
+            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+        </epc_section>
+        <memory>
+            <start_hpa desc="The start physical address in host for the VM">0x100000000</start_hpa>
+            <size desc="The memory size in Bytes for the VM">0x20000000</size>
+            <start_hpa2 configurable="0" desc="Start of second HPA for non-contiguous allocations in host for the VM">0x0</start_hpa2>
+            <size_hpa2 configurable="0" desc="Memory size of second HPA for non-contiguous allocations in Bytes for the VM">0x0</size_hpa2>
+        </memory>
+        <os_config>
+            <name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">Zephyr</name>
+            <kern_type desc="Specify the kernel image type so that hypervisor could load it correctly. Currently support KERNEL_BZIMAGE and KERNEL_ZEPHYR.">KERNEL_ZEPHYR</kern_type>
+            <kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">Zephyr_RawImage</kern_mod>
+            <ramdisk_mod desc="The tag for ramdisk image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline." />
+            <bootargs desc="Specify kernel boot arguments">reboot=acpi</bootargs>
+            <kern_load_addr desc="The loading address in host memory for the VM kernel">0x8000</kern_load_addr>
+            <kern_entry_addr desc="The entry address in host memory for the VM kernel">0x8000</kern_entry_addr>
+        </os_config>
+        <legacy_vuart id="0">
+            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
+            <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+        </legacy_vuart>
+        <legacy_vuart id="1">
+            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM2_BASE</base>
+            <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
+        </legacy_vuart>
+        <console_vuart id="0">
+            <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        </console_vuart>
+        <communication_vuart id="1">
+            <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+            <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+            <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+        </communication_vuart>
+        <pci_devs desc="pci devices list">
+            <pci_dev desc="pci device" />
+        </pci_devs>
+        <mmio_resources desc="mmio devices list to passthrough">
+            <TPM2 desc="TPM2 device">n</TPM2>
+            <p2sb>n</p2sb>
+        </mmio_resources>
+    </vm>
+    <vm id="1">
+        <vm_type desc="Specify the VM type" readonly="true">SOS_VM</vm_type>
+        <name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN SOS VM</name>
+        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+            <guest_flag>0</guest_flag>
+        </guest_flags>
+        <cpu_affinity desc="List of pCPU that this VM's vCPUs are pinned to.">
+            <pcpu_id>0</pcpu_id>
+            <pcpu_id>1</pcpu_id>
+            <pcpu_id>2</pcpu_id>
+        </cpu_affinity>
+        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+            <vcpu_clos>0</vcpu_clos>
+            <vcpu_clos>0</vcpu_clos>
+            <vcpu_clos>0</vcpu_clos>
+        </clos>
+        <memory>
+            <start_hpa configurable="0" desc="The start physical address in host for the VM">0</start_hpa>
+            <size configurable="0" desc="The memory size in Bytes for the VM">CONFIG_SOS_RAM_SIZE</size>
+        </memory>
+        <os_config>
+            <name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">ACRN Service OS</name>
+            <kern_type desc="Specify the kernel image type so that hypervisor could load it correctly. Currently support KERNEL_BZIMAGE and KERNEL_ZEPHYR.">KERNEL_BZIMAGE</kern_type>
+            <kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">Linux_bzImage</kern_mod>
+            <ramdisk_mod desc="The tag for ramdisk image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline." />
+            <bootargs configurable="0" desc="Specify kernel boot arguments">SOS_VM_BOOTARGS</bootargs>
+        </os_config>
+        <legacy_vuart id="0">
+            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">SOS_COM1_BASE</base>
+            <irq configurable="0" desc="vCOM1 irq">SOS_COM1_IRQ</irq>
+        </legacy_vuart>
+        <legacy_vuart id="1">
+            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">SOS_COM2_BASE</base>
+            <irq configurable="0" desc="vCOM2 irq">SOS_COM2_IRQ</irq>
+            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
+        </legacy_vuart>
+        <console_vuart id="0">
+            <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        </console_vuart>
+        <communication_vuart id="1">
+            <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+            <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+            <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+        </communication_vuart>
+        <pci_devs configurable="0" desc="pci devices list">
+            <pci_dev desc="pci device" />
+        </pci_devs>
+        <board_private>
+            <rootfs desc="rootfs for Linux kernel">/dev/sda3</rootfs>
+            <bootargs desc="Specify kernel boot arguments">
+        rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3
+        i915.nuclear_pageflip=1 swiotlb=131072
+        </bootargs>
+        </board_private>
+    </vm>
+    <vm id="2">
+        <vm_type desc="Specify the VM type" readonly="true">POST_STD_VM</vm_type>
+        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+            <guest_flag>0</guest_flag>
+        </guest_flags>
+        <cpu_affinity desc="List of pCPU: the guest VM is allowed to create vCPU from all or a subset of this list.">
+            <pcpu_id>2</pcpu_id>
+        </cpu_affinity>
+        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+            <vcpu_clos>0</vcpu_clos>
+        </clos>
+        <epc_section configurable="0" desc="epc section">
+            <base desc="SGX EPC section base, must be page aligned">0</base>
+            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+        </epc_section>
+        <legacy_vuart id="0">
+            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
+            <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+        </legacy_vuart>
+        <legacy_vuart id="1">
+            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
+            <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">0</target_uart_id>
+        </legacy_vuart>
+        <console_vuart id="0">
+            <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        </console_vuart>
+        <communication_vuart id="1">
+            <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+            <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+            <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+        </communication_vuart>
+    </vm>
+</acrn-config>

misc/config_tools/data/generic/hybrid_rt.xml

@@ -0,0 +1,261 @@
+<?xml version='1.0' encoding='utf-8'?>
+<acrn-config board="generic" scenario="hybrid_rt">
+    <hv>
+        <DEBUG_OPTIONS desc="Debug options for ACRN hypervisor, only valid on debug version">
+            <RELEASE desc="Release build. 'y' for Release, 'n' for Debug.">n</RELEASE>
+            <SERIAL_CONSOLE desc="The serial device which is used for hypervisor debug, only valid on Debug version.">/dev/ttyS0</SERIAL_CONSOLE>
+            <MEM_LOGLEVEL desc="Default loglevel in memory">5</MEM_LOGLEVEL>
+            <NPK_LOGLEVEL desc="Default loglevel for the hypervisor NPK log">5</NPK_LOGLEVEL>
+            <CONSOLE_LOGLEVEL desc="Default loglevel on the serial console">3</CONSOLE_LOGLEVEL>
+            <LOG_DESTINATION desc="Bitmap of consoles where logs are printed.">7</LOG_DESTINATION>
+            <LOG_BUF_SIZE desc="Capacity of logbuf for each physical cpu.">0x40000</LOG_BUF_SIZE>
+        </DEBUG_OPTIONS>
+        <FEATURES>
+            <RELOC desc="Enable hypervisor relocation">y</RELOC>
+            <SCHEDULER desc="The CPU scheduler to be used by the hypervisor.">SCHED_BVT</SCHEDULER>
+            <MULTIBOOT2 desc="Support boot ACRN from multiboot2 protocol.">y</MULTIBOOT2>
+            <RDT desc="Intel RDT (Resource Director Technology).">
+                <RDT_ENABLED desc="Enable RDT">n</RDT_ENABLED>
+                <CDP_ENABLED desc="CDP (Code and Data Prioritization). CDP is an extension of CAT.">n</CDP_ENABLED>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+            </RDT>
+            <HYPERV_ENABLED desc="Enable Hyper-V enlightenment">y</HYPERV_ENABLED>
+            <IOMMU_ENFORCE_SNP desc="IOMMU enforce snoop behavior of DMA operation.">n</IOMMU_ENFORCE_SNP>
+            <ACPI_PARSE_ENABLED desc="Enable ACPI runtime parsing.">y</ACPI_PARSE_ENABLED>
+            <L1D_VMENTRY_ENABLED desc="Enable L1 cache flush before VM entry.">n</L1D_VMENTRY_ENABLED>
+            <MCE_ON_PSC_DISABLED desc="Force to disable software workaround for Machine Check Error on Page Size Change.">n</MCE_ON_PSC_DISABLED>
+            <IVSHMEM desc="IVSHMEM configuration">
+                <IVSHMEM_ENABLED desc="Enable Share Memory between VMs by IVSHMEM.">y</IVSHMEM_ENABLED>
+                <IVSHMEM_REGION desc="the shared memory region name (starting with hv:/, size (in MB), and IDs of all VMs (separated by a colon) sharing this region, for example hv:/sharename,2,0:2">hv:/shm_region_0, 2, 0:2</IVSHMEM_REGION>
+            </IVSHMEM>
+        </FEATURES>
+        <MEMORY>
+            <STACK_SIZE desc="Capacity of one stack, in bytes.">0x2000</STACK_SIZE>
+            <HV_RAM_SIZE desc="Size of the RAM region used by the hypervisor" />
+            <HV_RAM_START desc="2M-aligned Start physical address of the RAM region used by the hypervisor." />
+            <LOW_RAM_SIZE desc="Size of the low RAM region">0x00010000</LOW_RAM_SIZE>
+            <UOS_RAM_SIZE desc="Size of the User OS (UOS) RAM.">0x200000000</UOS_RAM_SIZE>
+            <SOS_RAM_SIZE desc="Size of the Service OS (SOS) RAM.">0x400000000</SOS_RAM_SIZE>
+            <PLATFORM_RAM_SIZE desc="Size of the physical platform RAM">0x400000000</PLATFORM_RAM_SIZE>
+        </MEMORY>
+        <CAPACITIES desc="Capacity limits for static assigned data struct or maximum supported resouce">
+            <IOMMU_BUS_NUM desc="Highest PCI bus ID used during IOMMU initialization.">0x100</IOMMU_BUS_NUM>
+            <MAX_IR_ENTRIES desc="Maximum number of Interrupt Remapping Entries.">256</MAX_IR_ENTRIES>
+            <MAX_IOAPIC_NUM desc="Maximum number of IO-APICs.">1</MAX_IOAPIC_NUM>
+            <MAX_PCI_DEV_NUM desc="Maximum number of PCI devices.">96</MAX_PCI_DEV_NUM>
+            <MAX_IOAPIC_LINES desc="Maximum number of interrupt lines per IOAPIC.">120</MAX_IOAPIC_LINES>
+            <MAX_PT_IRQ_ENTRIES desc="Maximum number of interrupt source for PT devices.">256</MAX_PT_IRQ_ENTRIES>
+            <MAX_MSIX_TABLE_NUM desc="Maximum number of MSI-X tables per device. Please leave it blank if not sure.">64</MAX_MSIX_TABLE_NUM>
+            <MAX_EMULATED_MMIO desc="Maximum number of emulated MMIO regions.">16</MAX_EMULATED_MMIO>
+        </CAPACITIES>
+        <MISC_CFG>
+            <GPU_SBDF desc="Segment, Bus, Device, and function of the GPU.">0x00000010</GPU_SBDF>
+            <UEFI_OS_LOADER_NAME desc="UEFI OS loader name."></UEFI_OS_LOADER_NAME>
+        </MISC_CFG>
+    </hv>
+    <vm id="0">
+        <vm_type desc="Specify the VM type" readonly="true">PRE_RT_VM</vm_type>
+        <name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN PRE-LAUNCHED VM0</name>
+        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+            <guest_flag>GUEST_FLAG_LAPIC_PASSTHROUGH</guest_flag>
+            <guest_flag>GUEST_FLAG_RT</guest_flag>
+        </guest_flags>
+        <cpu_affinity desc="List of pCPU that this VM's vCPUs are pinned to.">
+            <pcpu_id>2</pcpu_id>
+            <pcpu_id>3</pcpu_id>
+        </cpu_affinity>
+        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+            <vcpu_clos>0</vcpu_clos>
+            <vcpu_clos>0</vcpu_clos>
+        </clos>
+        <epc_section configurable="0" desc="epc section">
+            <base desc="SGX EPC section base, must be page aligned">0</base>
+            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+        </epc_section>
+        <memory>
+            <start_hpa desc="The start physical address in host for the VM">0x100000000</start_hpa>
+            <size desc="The memory size in Bytes for the VM">0x40000000</size>
+            <start_hpa2 configurable="0" desc="Start of second HPA for non-contiguous allocations in host for the VM">0x0</start_hpa2>
+            <size_hpa2 configurable="0" desc="Memory size of second HPA for non-contiguous allocations in Bytes for the VM">0x0</size_hpa2>
+        </memory>
+        <os_config>
+            <name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">PREEMPT-RT</name>
+            <kern_type desc="Specify the kernel image type so that hypervisor could load it correctly. Currently support KERNEL_BZIMAGE and KERNEL_ZEPHYR.">KERNEL_BZIMAGE</kern_type>
+            <kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">RT_bzImage</kern_mod>
+            <ramdisk_mod desc="The tag for ramdisk image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline." />
+            <bootargs desc="Specify kernel boot arguments">rw rootwait root=/dev/sda3 no_ipi_broadcast=1 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel consoleblank=0 tsc=reliable clocksource=tsc x2apic_phys processor.max_cstate=0 intel_idle.max_cstate=0 intel_pstate=disable mce=ignore_ce audit=0 isolcpus=nohz,domain,1 nohz_full=1 rcu_nocbs=1 nosoftlockup idle=poll irqaffinity=0 reboot=acpi </bootargs>
+        </os_config>
+        <legacy_vuart id="0">
+            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
+            <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+        </legacy_vuart>
+        <legacy_vuart id="1">
+            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM2_BASE</base>
+            <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
+        </legacy_vuart>
+        <console_vuart id="0">
+            <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        </console_vuart>
+        <communication_vuart id="1">
+            <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+            <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+            <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+        </communication_vuart>
+        <pci_devs desc="pci devices list">
+            <pci_dev desc="pci device">00:17.0 SATA controller: Intel Corporation Device 4b63</pci_dev>
+            <pci_dev desc="pci device">00:1d.2 Ethernet controller: Intel Corporation Device 4bb0</pci_dev>
+        </pci_devs>
+        <mmio_resources desc="mmio devices list to passthrough">
+            <TPM2 desc="TPM2 device">y</TPM2>
+        </mmio_resources>
+    </vm>
+    <vm id="1">
+        <vm_type desc="Specify the VM type" readonly="true">SOS_VM</vm_type>
+        <name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN SOS VM</name>
+        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+            <guest_flag>0</guest_flag>
+        </guest_flags>
+        <cpu_affinity desc="List of pCPU that this VM's vCPUs are pinned to.">
+            <pcpu_id>0</pcpu_id>
+            <pcpu_id>1</pcpu_id>
+        </cpu_affinity>
+        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+            <vcpu_clos>0</vcpu_clos>
+            <vcpu_clos>0</vcpu_clos>
+        </clos>
+        <memory>
+            <start_hpa configurable="0" desc="The start physical address in host for the VM">0</start_hpa>
+            <size configurable="0" desc="The memory size in Bytes for the VM">CONFIG_SOS_RAM_SIZE</size>
+        </memory>
+        <os_config>
+            <name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">ACRN Service OS</name>
+            <kern_type desc="Specify the kernel image type so that hypervisor could load it correctly. Currently support KERNEL_BZIMAGE and KERNEL_ZEPHYR.">KERNEL_BZIMAGE</kern_type>
+            <kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">Linux_bzImage</kern_mod>
+            <ramdisk_mod desc="The tag for ramdisk image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline." />
+            <bootargs configurable="0" desc="Specify kernel boot arguments">SOS_VM_BOOTARGS</bootargs>
+        </os_config>
+        <legacy_vuart id="0">
+            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">SOS_COM1_BASE</base>
+            <irq configurable="0" desc="vCOM1 irq">SOS_COM1_IRQ</irq>
+        </legacy_vuart>
+        <legacy_vuart id="1">
+            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">SOS_COM2_BASE</base>
+            <irq configurable="0" desc="vCOM2 irq">SOS_COM2_IRQ</irq>
+            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
+        </legacy_vuart>
+        <console_vuart id="0">
+            <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        </console_vuart>
+        <communication_vuart id="1">
+            <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+            <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+            <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+        </communication_vuart>
+        <pci_devs configurable="0" desc="pci devices list">
+            <pci_dev desc="pci device" />
+        </pci_devs>
+        <board_private>
+            <rootfs desc="rootfs for Linux kernel">/dev/nvme0n1p3</rootfs>
+            <bootargs desc="Specify kernel boot arguments">
+            rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3
+            i915.nuclear_pageflip=1 swiotlb=131072
+            </bootargs>
+        </board_private>
+    </vm>
+    <vm id="2">
+        <vm_type desc="Specify the VM type" readonly="true">POST_STD_VM</vm_type>
+        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+            <guest_flag>0</guest_flag>
+        </guest_flags>
+        <cpu_affinity desc="List of pCPU: the guest VM is allowed to create vCPU from all or a subset of this list.">
+            <pcpu_id>0</pcpu_id>
+            <pcpu_id>1</pcpu_id>
+        </cpu_affinity>
+        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+            <vcpu_clos>0</vcpu_clos>
+            <vcpu_clos>0</vcpu_clos>
+        </clos>
+        <epc_section configurable="0" desc="epc section">
+            <base desc="SGX EPC section base, must be page aligned">0</base>
+            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+        </epc_section>
+        <legacy_vuart id="0">
+            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
+            <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+        </legacy_vuart>
+        <legacy_vuart id="1">
+            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
+            <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">0</target_uart_id>
+        </legacy_vuart>
+        <console_vuart id="0">
+            <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        </console_vuart>
+        <communication_vuart id="1">
+            <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+            <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+            <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+        </communication_vuart>
+    </vm>
+    <vm id="3">
+        <vm_type desc="Specify the VM type" readonly="true">POST_STD_VM</vm_type>
+        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+            <guest_flag>0</guest_flag>
+        </guest_flags>
+        <cpu_affinity desc="List of pCPU: the guest VM is allowed to create vCPU from all or a subset of this list.">
+            <pcpu_id>1</pcpu_id>
+        </cpu_affinity>
+        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+            <vcpu_clos>0</vcpu_clos>
+        </clos>
+        <epc_section configurable="0" desc="epc section">
+            <base desc="SGX EPC section base, must be page aligned">0</base>
+            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+        </epc_section>
+        <legacy_vuart id="0">
+            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
+            <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+        </legacy_vuart>
+        <legacy_vuart id="1">
+            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
+            <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">0</target_uart_id>
+        </legacy_vuart>
+        <console_vuart id="0">
+            <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        </console_vuart>
+        <communication_vuart id="1">
+            <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+            <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+            <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+        </communication_vuart>
+    </vm>
+</acrn-config>

misc/config_tools/data/generic/industry.xml

@@ -0,0 +1,384 @@
+<?xml version='1.0' encoding='utf-8'?>
+<acrn-config board="generic" scenario="industry">
+    <hv>
+        <DEBUG_OPTIONS desc="Debug options for ACRN hypervisor, only valid on debug version">
+            <RELEASE desc="Release build. 'y' for Release, 'n' for Debug.">n</RELEASE>
+            <SERIAL_CONSOLE desc="The serial device which is used for hypervisor debug, only valid on Debug version.">/dev/ttyS3</SERIAL_CONSOLE>
+            <MEM_LOGLEVEL desc="Default loglevel in memory">5</MEM_LOGLEVEL>
+            <NPK_LOGLEVEL desc="Default loglevel for the hypervisor NPK log">5</NPK_LOGLEVEL>
+            <CONSOLE_LOGLEVEL desc="Default loglevel on the serial console">3</CONSOLE_LOGLEVEL>
+            <LOG_DESTINATION desc="Bitmap of consoles where logs are printed.">7</LOG_DESTINATION>
+            <LOG_BUF_SIZE desc="Capacity of logbuf for each physical cpu.">0x40000</LOG_BUF_SIZE>
+        </DEBUG_OPTIONS>
+        <FEATURES>
+            <RELOC desc="Enable hypervisor relocation">y</RELOC>
+            <SCHEDULER desc="The CPU scheduler to be used by the hypervisor.">SCHED_BVT</SCHEDULER>
+            <MULTIBOOT2 desc="Support boot ACRN from multiboot2 protocol.">y</MULTIBOOT2>
+            <RDT desc="Intel RDT (Resource Director Technology).">
+                <RDT_ENABLED desc="Enable RDT">y</RDT_ENABLED>
+                <CDP_ENABLED desc="CDP (Code and Data Prioritization). CDP is an extension of CAT.">n</CDP_ENABLED>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+            </RDT>
+            <HYPERV_ENABLED desc="Enable Hyper-V enlightenment">y</HYPERV_ENABLED>
+            <IOMMU_ENFORCE_SNP desc="IOMMU enforce snoop behavior of DMA operation.">n</IOMMU_ENFORCE_SNP>
+            <ACPI_PARSE_ENABLED desc="Enable ACPI runtime parsing.">y</ACPI_PARSE_ENABLED>
+            <L1D_VMENTRY_ENABLED desc="Enable L1 cache flush before VM entry.">n</L1D_VMENTRY_ENABLED>
+            <MCE_ON_PSC_DISABLED desc="Force to disable software workaround for Machine Check Error on Page Size Change.">n</MCE_ON_PSC_DISABLED>
+            <IVSHMEM desc="IVSHMEM configuration">
+                <IVSHMEM_ENABLED desc="Enable Share Memory between VMs by IVSHMEM.">n</IVSHMEM_ENABLED>
+                <IVSHMEM_REGION desc="the shared memory region name (starting with hv:/, size (in MB), and IDs of all VMs (separated by a colon) sharing this region, for example hv:/sharename,2,0:2"></IVSHMEM_REGION>
+            </IVSHMEM>
+        </FEATURES>
+        <MEMORY>
+            <STACK_SIZE desc="Capacity of one stack, in bytes.">0x2000</STACK_SIZE>
+            <HV_RAM_SIZE desc="Size of the RAM region used by the hypervisor" />
+            <HV_RAM_START desc="2M-aligned Start physical address of the RAM region used by the hypervisor." />
+            <LOW_RAM_SIZE desc="Size of the low RAM region">0x00010000</LOW_RAM_SIZE>
+            <UOS_RAM_SIZE desc="Size of the User OS (UOS) RAM.">0x200000000</UOS_RAM_SIZE>
+            <SOS_RAM_SIZE desc="Size of the Service OS (SOS) RAM.">0x400000000</SOS_RAM_SIZE>
+            <PLATFORM_RAM_SIZE desc="Size of the physical platform RAM">0x400000000</PLATFORM_RAM_SIZE>
+        </MEMORY>
+        <CAPACITIES desc="Capacity limits for static assigned data struct or maximum supported resouce">
+            <IOMMU_BUS_NUM desc="Highest PCI bus ID used during IOMMU initialization.">0x100</IOMMU_BUS_NUM>
+            <MAX_IR_ENTRIES desc="Maximum number of Interrupt Remapping Entries.">256</MAX_IR_ENTRIES>
+            <MAX_IOAPIC_NUM desc="Maximum number of IO-APICs.">1</MAX_IOAPIC_NUM>
+            <MAX_PCI_DEV_NUM desc="Maximum number of PCI devices.">96</MAX_PCI_DEV_NUM>
+            <MAX_IOAPIC_LINES desc="Maximum number of interrupt lines per IOAPIC.">120</MAX_IOAPIC_LINES>
+            <MAX_PT_IRQ_ENTRIES desc="Maximum number of interrupt source for PT devices.">256</MAX_PT_IRQ_ENTRIES>
+            <MAX_MSIX_TABLE_NUM desc="Maximum number of MSI-X tables per device. Please leave it blank if not sure.">64</MAX_MSIX_TABLE_NUM>
+            <MAX_EMULATED_MMIO desc="Maximum number of emulated MMIO regions.">16</MAX_EMULATED_MMIO>
+        </CAPACITIES>
+        <MISC_CFG>
+            <GPU_SBDF desc="Segment, Bus, Device, and function of the GPU.">0x00000010</GPU_SBDF>
+        </MISC_CFG>
+    </hv>
+    <vm id="0">
+        <vm_type desc="Specify the VM type" readonly="true">SOS_VM</vm_type>
+        <name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN SOS VM</name>
+        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+            <guest_flag>0</guest_flag>
+        </guest_flags>
+        <clos configurable="0" desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+            <vcpu_clos>0</vcpu_clos>
+        </clos>
+        <memory>
+            <start_hpa configurable="0" desc="The start physical address in host for the VM">0</start_hpa>
+            <size configurable="0" desc="The memory size in Bytes for the VM">0x20000000</size>
+        </memory>
+        <os_config>
+            <name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">ACRN Service OS</name>
+            <kern_type desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">KERNEL_BZIMAGE</kern_type>
+            <kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">Linux_bzImage</kern_mod>
+            <ramdisk_mod desc="The tag for ramdisk image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline." />
+            <bootargs configurable="0" desc="Specify kernel boot arguments">SOS_VM_BOOTARGS</bootargs>
+        </os_config>
+        <legacy_vuart id="0">
+            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">SOS_COM1_BASE</base>
+            <irq configurable="0" desc="vCOM1 irq">SOS_COM1_IRQ</irq>
+        </legacy_vuart>
+        <legacy_vuart id="1">
+            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">SOS_COM2_BASE</base>
+            <irq configurable="0" desc="vCOM2 irq">SOS_COM2_IRQ</irq>
+            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">2</target_vm_id>
+            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
+        </legacy_vuart>
+        <console_vuart id="0">
+            <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        </console_vuart>
+        <communication_vuart id="1">
+            <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+            <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+            <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+        </communication_vuart>
+        <pci_devs configurable="0" desc="pci devices list">
+            <pci_dev desc="pci device" />
+        </pci_devs>
+        <board_private>
+            <rootfs desc="rootfs for Linux kernel">/dev/nvme0n1p3</rootfs>
+            <bootargs desc="Specify kernel boot arguments">
+        rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3
+        i915.nuclear_pageflip=1 swiotlb=131072
+        </bootargs>
+        </board_private>
+    </vm>
+    <vm id="1">
+        <vm_type desc="Specify the VM type" readonly="true">POST_STD_VM</vm_type>
+        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+            <guest_flag>0</guest_flag>
+        </guest_flags>
+        <cpu_affinity desc="List of pCPU: the guest VM is allowed to create vCPU from all or a subset of this list.">
+            <pcpu_id>0</pcpu_id>
+            <pcpu_id>1</pcpu_id>
+        </cpu_affinity>
+        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+            <vcpu_clos>0</vcpu_clos>
+            <vcpu_clos>0</vcpu_clos>
+        </clos>
+        <epc_section configurable="0" desc="epc section">
+            <base desc="SGX EPC section base, must be page aligned">0</base>
+            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+        </epc_section>
+        <legacy_vuart id="0">
+            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
+            <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+        </legacy_vuart>
+        <legacy_vuart id="1">
+            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
+            <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
+        </legacy_vuart>
+        <console_vuart id="0">
+            <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        </console_vuart>
+        <communication_vuart id="1">
+            <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+            <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+            <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+        </communication_vuart>
+    </vm>
+    <vm id="2">
+        <vm_type desc="Specify the VM type" readonly="true">POST_RT_VM</vm_type>
+        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+            <guest_flag>0</guest_flag>
+        </guest_flags>
+        <cpu_affinity desc="List of pCPU: the guest VM is allowed to create vCPU from all or a subset of this list.">
+            <pcpu_id>2</pcpu_id>
+            <pcpu_id>3</pcpu_id>
+        </cpu_affinity>
+        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+            <vcpu_clos>0</vcpu_clos>
+            <vcpu_clos>0</vcpu_clos>
+        </clos>
+        <epc_section configurable="0" desc="epc section">
+            <base desc="SGX EPC section base, must be page aligned">0</base>
+            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+        </epc_section>
+        <legacy_vuart id="0">
+            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
+            <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+        </legacy_vuart>
+        <legacy_vuart id="1">
+            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM2_BASE</base>
+            <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
+        </legacy_vuart>
+        <console_vuart id="0">
+            <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        </console_vuart>
+        <communication_vuart id="1">
+            <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+            <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+            <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+        </communication_vuart>
+  </vm>
+  <vm id="3">
+    <vm_type desc="Specify the VM type" readonly="true">POST_STD_VM</vm_type>
+    <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+        <guest_flag>0</guest_flag>
+    </guest_flags>
+    <cpu_affinity desc="List of pCPU: the guest VM is allowed to create vCPU from all or a subset of this list.">
+        <pcpu_id>0</pcpu_id>
+        <pcpu_id>1</pcpu_id>
+    </cpu_affinity>
+    <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+        <vcpu_clos>0</vcpu_clos>
+        <vcpu_clos>0</vcpu_clos>
+    </clos>
+    <epc_section configurable="0" desc="epc section">
+        <base desc="SGX EPC section base, must be page aligned">0</base>
+        <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+    </epc_section>
+    <legacy_vuart id="0">
+        <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+        <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
+        <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+    </legacy_vuart>
+    <legacy_vuart id="1">
+        <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+        <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
+        <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+        <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+        <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
+    </legacy_vuart>
+    <console_vuart id="0">
+        <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+    </console_vuart>
+    <communication_vuart id="1">
+        <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+        <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+    </communication_vuart>
+  </vm>
+  <vm id="4">
+    <vm_type desc="Specify the VM type" readonly="true">POST_STD_VM</vm_type>
+    <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+        <guest_flag>0</guest_flag>
+    </guest_flags>
+    <cpu_affinity desc="List of pCPU: the guest VM is allowed to create vCPU from all or a subset of this list.">
+        <pcpu_id>0</pcpu_id>
+        <pcpu_id>1</pcpu_id>
+    </cpu_affinity>
+    <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+        <vcpu_clos>0</vcpu_clos>
+        <vcpu_clos>0</vcpu_clos>
+    </clos>
+    <epc_section configurable="0" desc="epc section">
+        <base desc="SGX EPC section base, must be page aligned">0</base>
+        <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+    </epc_section>
+    <legacy_vuart id="0">
+        <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+        <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
+        <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+    </legacy_vuart>
+    <legacy_vuart id="1">
+        <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+        <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
+        <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+        <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+        <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
+    </legacy_vuart>
+    <console_vuart id="0">
+        <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+    </console_vuart>
+    <communication_vuart id="1">
+        <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+        <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+    </communication_vuart>
+  </vm>
+  <vm id="5">
+    <vm_type desc="Specify the VM type" readonly="true">POST_STD_VM</vm_type>
+    <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+        <guest_flag>0</guest_flag>
+    </guest_flags>
+    <cpu_affinity desc="List of pCPU: the guest VM is allowed to create vCPU from all or a subset of this list.">
+        <pcpu_id>0</pcpu_id>
+        <pcpu_id>1</pcpu_id>
+    </cpu_affinity>
+    <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+        <vcpu_clos>0</vcpu_clos>
+        <vcpu_clos>0</vcpu_clos>
+    </clos>
+    <epc_section configurable="0" desc="epc section">
+        <base desc="SGX EPC section base, must be page aligned">0</base>
+        <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+    </epc_section>
+    <legacy_vuart id="0">
+        <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+        <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
+        <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+    </legacy_vuart>
+    <legacy_vuart id="1">
+        <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+        <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
+        <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+        <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+        <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
+    </legacy_vuart>
+    <console_vuart id="0">
+        <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+    </console_vuart>
+    <communication_vuart id="1">
+        <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+        <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+    </communication_vuart>
+  </vm>
+  <vm id="6">
+    <vm_type desc="Specify the VM type" readonly="true">POST_STD_VM</vm_type>
+    <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+        <guest_flag>0</guest_flag>
+    </guest_flags>
+    <cpu_affinity desc="List of pCPU: the guest VM is allowed to create vCPU from all or a subset of this list.">
+        <pcpu_id>0</pcpu_id>
+        <pcpu_id>1</pcpu_id>
+    </cpu_affinity>
+    <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+        <vcpu_clos>0</vcpu_clos>
+        <vcpu_clos>0</vcpu_clos>
+    </clos>
+    <epc_section configurable="0" desc="epc section">
+        <base desc="SGX EPC section base, must be page aligned">0</base>
+        <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+    </epc_section>
+    <legacy_vuart id="0">
+        <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+        <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
+        <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+    </legacy_vuart>
+    <legacy_vuart id="1">
+        <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+        <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
+        <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+        <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+        <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
+    </legacy_vuart>
+    <console_vuart id="0">
+        <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+    </console_vuart>
+    <communication_vuart id="1">
+        <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+        <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+    </communication_vuart>
+  </vm>
+  <vm id="7" configurable="1" desc="specific for Kata">
+    <vm_type readonly="true" desc="Specify the VM type">KATA_VM</vm_type>
+    <cpu_affinity desc="List of pCPU: the guest VM is allowed to create vCPU from all or a subset of this list.">
+        <pcpu_id>0</pcpu_id>
+        <pcpu_id>1</pcpu_id>
+    </cpu_affinity>
+    <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+        <vcpu_clos>0</vcpu_clos>
+        <vcpu_clos>0</vcpu_clos>
+    </clos>
+    <epc_section configurable="0" desc="epc section">
+        <base desc="SGX EPC section base, must be page aligned">0</base>
+        <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+    </epc_section>
+    <legacy_vuart id="0">
+        <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+        <base configurable="0" desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
+        <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+    </legacy_vuart>
+    <legacy_vuart id="1">
+        <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+        <base configurable="0" desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_COM_BASE</base>
+        <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+        <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+        <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">0</target_uart_id>
+    </legacy_vuart>
+    <console_vuart id="0">
+        <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+    </console_vuart>
+    <communication_vuart id="1">
+        <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+        <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+    </communication_vuart>
+  </vm>
+</acrn-config>

misc/config_tools/data/generic/industry_launch_2uos.xml

@@ -1,9 +1,9 @@
 <acrn-config board="generic" scenario="industry" uos_launcher="2">
     <uos id="1">
-	<uos_type desc="UOS type"></uos_type>
-	<rtos_type desc="UOS Realtime capability"></rtos_type>
-	<mem_size desc="UOS memory size in MByte"></mem_size>
-	<gvt_args desc="GVT arguments. Recommendation is 64 448 8. Leave it blank to disable GVT."></gvt_args>
+	<uos_type desc="UOS type">WINDOWS</uos_type>
+	<rtos_type desc="UOS Realtime capability">no</rtos_type>
+	<mem_size desc="UOS memory size in MByte">4096</mem_size>
+	<gvt_args desc="GVT settings. Set it to gvtd for GVTd, otherwise is GVTg arguments. The recommendation arguments for GVTg is 64 448 8. Leave it blank to disable GVT.">gvtd</gvt_args>
 	<vbootloader desc="virtual bootloader method" readonly="true">ovmf</vbootloader>
 	<vuart0 desc="vUART0 which emulated by device model">Enable</vuart0>
 	<poweroff_channel desc="the method of power off uos"></poweroff_channel>
@@ -20,7 +20,7 @@
 	</communication_vuarts>
 	<passthrough_devices>
 		<usb_xdci desc="vm usb_xdci device"></usb_xdci>
-		<audio desc="vm audio device"></audio>
+		<audio desc="vm audio device">00:1f.3 Multimedia audio controller: Intel Corporation Device 4b58</audio>
 		<audio_codec desc="vm audio codec device"></audio_codec>
 		<ipu desc="vm ipu device"></ipu>
 		<ipu_i2c desc="vm ipu_i2c device"></ipu_i2c>
@@ -34,20 +34,21 @@
 	</passthrough_devices>
 
 	<virtio_devices>
-		<network desc="virtio network devices setting. Input format: tap_name,[vhost],[mac=XX:XX:XX:XX:XX:XX]."></network>
+		<network desc="virtio network devices setting. Input format: tap_name,[vhost],[mac=XX:XX:XX:XX:XX:XX].">WaaG</network>
 		<input desc="virtio input device"></input>
-		<block desc="virtio block device setting. format: [blk partition:][img path] e.g.: /dev/sda3:./a/b.img"></block>
+		<block desc="virtio block device setting. format: [blk partition:][img path] e.g.: /dev/sda3:./a/b.img">./win10-ltsc.img</block>
 		<console desc="virtio console device,input format: [@]stdio|tty|pty|sock:portname[=portpath][,[@]stdio|tty|pty:portname[=portpath]]"></console>
 	</virtio_devices>
     </uos>
+
     <uos id="2">
-	<uos_type desc="UOS type"></uos_type>
-	<rtos_type desc="UOS Realtime capability"></rtos_type>
-	<mem_size desc="UOS memory size in MByte"></mem_size>
-	<gvt_args desc="GVT arguments. Recommendation is 64 448 8. Leave it blank to disable GVT."></gvt_args>
+	<uos_type desc="UOS type">PREEMPT-RT LINUX</uos_type>
+	<rtos_type desc="UOS Realtime capability">Hard RT</rtos_type>
+	<mem_size desc="UOS memory size in MByte">1024</mem_size>
+	<gvt_args configurable="0" desc="GVT settings. Set it to gvtd for GVTd, otherwise is GVTg arguments. The recommendation arguments for GVTg is 64 448 8. Leave it blank to disable GVT."></gvt_args>
 	<vbootloader desc="virtual bootloader method" readonly="true">ovmf</vbootloader>
 	<vuart0 desc="vUART0 which emulated by device model">Disable</vuart0>
-	<poweroff_channel desc="the method of power off uos"></poweroff_channel>
+	<poweroff_channel desc="the method of power off uos">vuart1(tty)</poweroff_channel>
 	<usb_xhci desc="USB xHCI mediator configuration. input format: bus#-port#[:bus#-port#: ...]. e.g.: 1-2:2-4"></usb_xhci>
 	<cpu_affinity desc="List of pCPU that this VM's vCPUs are pinned to.">
 		<pcpu_id></pcpu_id>
@@ -78,7 +79,7 @@
 		<network desc="virtio network devices setting. Input format: tap_name,[vhost],[mac=XX:XX:XX:XX:XX:XX]."></network>
 		<input desc="virtio input device"></input>
 		<block desc="virtio block device setting. format: [blk partition:][img path] e.g.: /dev/sda3:./a/b.img"></block>
-		<console desc="virtio console device,input format: [@]stdio|tty|pty|sock:portname[=portpath][,[@]stdio|tty|pty:portname[=portpath]]"></console>
+		<console desc="virtio console device,input format: [@]stdio|tty|pty|sock:portname[=portpath][,[@]stdio|tty|pty:portname[=portpath]]">@stdio:stdio_port</console>
 	</virtio_devices>
     </uos>
 </acrn-config>

misc/config_tools/data/generic/logical_partition.xml

@@ -0,0 +1,194 @@
+<?xml version='1.0' encoding='utf-8'?>
+<acrn-config board="generic" scenario="logical_partition">
+    <hv>
+        <DEBUG_OPTIONS desc="Debug options for ACRN hypervisor, only valid on debug version">
+            <RELEASE desc="Release build. 'y' for Release, 'n' for Debug.">n</RELEASE>
+            <SERIAL_CONSOLE desc="The serial device which is used for hypervisor debug, only valid on Debug version.">/dev/ttyS0</SERIAL_CONSOLE>
+            <MEM_LOGLEVEL desc="Default loglevel in memory">5</MEM_LOGLEVEL>
+            <NPK_LOGLEVEL desc="Default loglevel for the hypervisor NPK log">5</NPK_LOGLEVEL>
+            <CONSOLE_LOGLEVEL desc="Default loglevel on the serial console">3</CONSOLE_LOGLEVEL>
+            <LOG_DESTINATION desc="Bitmap of consoles where logs are printed.">7</LOG_DESTINATION>
+            <LOG_BUF_SIZE desc="Capacity of logbuf for each physical cpu.">0x40000</LOG_BUF_SIZE>
+        </DEBUG_OPTIONS>
+        <FEATURES>
+            <RELOC desc="Enable hypervisor relocation">y</RELOC>
+            <SCHEDULER desc="The CPU scheduler to be used by the hypervisor.">SCHED_BVT</SCHEDULER>
+            <MULTIBOOT2 desc="Support boot ACRN from multiboot2 protocol.">y</MULTIBOOT2>
+            <RDT desc="Intel RDT (Resource Director Technology).">
+                <RDT_ENABLED desc="Enable RDT">n</RDT_ENABLED>
+                <CDP_ENABLED desc="CDP (Code and Data Prioritization). CDP is an extension of CAT.">n</CDP_ENABLED>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+                <CLOS_MASK desc="Cache Capacity Bitmask">0xfff</CLOS_MASK>
+            </RDT>
+            <HYPERV_ENABLED desc="Enable Hyper-V enlightenment">y</HYPERV_ENABLED>
+            <IOMMU_ENFORCE_SNP desc="IOMMU enforce snoop behavior of DMA operation.">n</IOMMU_ENFORCE_SNP>
+            <ACPI_PARSE_ENABLED desc="Enable ACPI runtime parsing.">y</ACPI_PARSE_ENABLED>
+            <L1D_VMENTRY_ENABLED desc="Enable L1 cache flush before VM entry.">n</L1D_VMENTRY_ENABLED>
+            <MCE_ON_PSC_DISABLED desc="Force to disable software workaround for Machine Check Error on Page Size Change.">n</MCE_ON_PSC_DISABLED>
+            <IVSHMEM desc="IVSHMEM configuration">
+                <IVSHMEM_ENABLED desc="Enable Share Memory between VMs by IVSHMEM.">n</IVSHMEM_ENABLED>
+                <IVSHMEM_REGION desc="the shared memory region name (starting with hv:/, size (in MB), and IDs of all VMs (separated by a colon) sharing this region, for example hv:/sharename,2,0:2"></IVSHMEM_REGION>
+            </IVSHMEM>
+        </FEATURES>
+        <MEMORY>
+            <STACK_SIZE desc="Capacity of one stack, in bytes.">0x2000</STACK_SIZE>
+            <HV_RAM_SIZE desc="Size of the RAM region used by the hypervisor" />
+            <HV_RAM_START desc="2M-aligned Start physical address of the RAM region used by the hypervisor." />
+            <LOW_RAM_SIZE desc="Size of the low RAM region">0x00010000</LOW_RAM_SIZE>
+            <UOS_RAM_SIZE desc="Size of the User OS (UOS) RAM.">0x200000000</UOS_RAM_SIZE>
+            <SOS_RAM_SIZE desc="Size of the Service OS (SOS) RAM.">0x400000000</SOS_RAM_SIZE>
+            <PLATFORM_RAM_SIZE desc="Size of the physical platform RAM">0x400000000</PLATFORM_RAM_SIZE>
+        </MEMORY>
+        <CAPACITIES desc="Capacity limits for static assigned data struct or maximum supported resouce">
+            <IOMMU_BUS_NUM desc="Highest PCI bus ID used during IOMMU initialization.">0x100</IOMMU_BUS_NUM>
+            <MAX_IR_ENTRIES desc="Maximum number of Interrupt Remapping Entries.">256</MAX_IR_ENTRIES>
+            <MAX_IOAPIC_NUM desc="Maximum number of IO-APICs.">1</MAX_IOAPIC_NUM>
+            <MAX_PCI_DEV_NUM desc="Maximum number of PCI devices.">96</MAX_PCI_DEV_NUM>
+            <MAX_IOAPIC_LINES desc="Maximum number of interrupt lines per IOAPIC.">120</MAX_IOAPIC_LINES>
+            <MAX_PT_IRQ_ENTRIES desc="Maximum number of interrupt source for PT devices.">64</MAX_PT_IRQ_ENTRIES>
+            <MAX_MSIX_TABLE_NUM desc="Maximum number of MSI-X tables per device. Please leave it blank if not sure.">64</MAX_MSIX_TABLE_NUM>
+            <MAX_EMULATED_MMIO desc="Maximum number of emulated MMIO regions.">16</MAX_EMULATED_MMIO>
+        </CAPACITIES>
+        <MISC_CFG>
+            <GPU_SBDF desc="Segment, Bus, Device, and function of the GPU.">0x00000010</GPU_SBDF>
+        </MISC_CFG>
+    </hv>
+    <vm id="0">
+        <vm_type desc="Specify the VM type" readonly="true">PRE_STD_VM</vm_type>
+        <name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN PRE-LAUNCHED VM0</name>
+        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+            <guest_flag />
+            <guest_flag />
+        </guest_flags>
+        <cpu_affinity desc="List of pCPU that this VM's vCPUs are pinned to.">
+            <pcpu_id>0</pcpu_id>
+            <pcpu_id>2</pcpu_id>
+        </cpu_affinity>
+        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+            <vcpu_clos>0</vcpu_clos>
+            <vcpu_clos>0</vcpu_clos>
+        </clos>
+        <epc_section configurable="0" desc="epc section">
+            <base desc="SGX EPC section base, must be page aligned">0</base>
+            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+        </epc_section>
+        <memory>
+            <start_hpa desc="The start physical address in host for the VM">0x100000000</start_hpa>
+            <size desc="The memory size in Bytes for the VM">0x20000000</size>
+            <start_hpa2 desc="Start of second HPA for non-contiguous allocations in host for the VM">0x0</start_hpa2>
+            <size_hpa2 desc="Memory size of second HPA for non-contiguous allocations in Bytes for the VM">0x0</size_hpa2>
+        </memory>
+        <os_config>
+            <name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">YOCTO</name>
+            <kern_type desc="Specify the kernel image type so that hypervisor could load it correctly. Currently support KERNEL_BZIMAGE and KERNEL_ZEPHYR.">KERNEL_BZIMAGE</kern_type>
+            <kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">Linux_bzImage</kern_mod>
+            <ramdisk_mod desc="The tag for ramdisk image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline." />
+            <bootargs desc="Specify kernel boot arguments">
+        rw rootwait root=/dev/sda3 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel log_buf_len=16M consoleblank=0 tsc=reliable reboot=acpi
+        </bootargs>
+        </os_config>
+        <legacy_vuart id="0">
+            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
+            <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+        </legacy_vuart>
+        <legacy_vuart id="1">
+            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM2_BASE</base>
+            <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
+        </legacy_vuart>
+        <console_vuart id="0">
+            <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        </console_vuart>
+        <communication_vuart id="1">
+            <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+            <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+            <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+        </communication_vuart>
+        <pci_devs desc="pci devices list">
+            <pci_dev desc="pci device" />
+            <pci_dev desc="pci device" />
+        </pci_devs>
+        <mmio_resources desc="mmio devices list to passthrough">
+            <TPM2 desc="TPM2 device">n</TPM2>
+        </mmio_resources>
+    </vm>
+    <vm id="1">
+        <vm_type desc="Specify the VM type" readonly="true">PRE_STD_VM</vm_type>
+        <name desc="vm_name">ACRN PRE-LAUNCHED VM1</name>
+        <guest_flags desc="Select all applicable flags for the VM" multiselect="true">
+            <guest_flag></guest_flag>
+        </guest_flags>
+        <cpu_affinity desc="List of pCPU that this VM's vCPUs are pinned to.">
+            <pcpu_id>1</pcpu_id>
+            <pcpu_id>3</pcpu_id>
+        </cpu_affinity>
+        <clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
+            <vcpu_clos>0</vcpu_clos>
+            <vcpu_clos>0</vcpu_clos>
+        </clos>
+        <epc_section configurable="0" desc="epc section">
+            <base desc="SGX EPC section base, must be page aligned">0</base>
+            <size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
+        </epc_section>
+        <memory>
+            <start_hpa desc="The start physical address in host for the VM">0x120000000</start_hpa>
+            <size desc="The memory size in Bytes for the VM">0x20000000</size>
+            <start_hpa2 desc="Start of second HPA for non-contiguous allocations in host for the VM">0x0</start_hpa2>
+            <size_hpa2 desc="Memory size of second HPA for non-contiguous allocations in Bytes for the VM">0x0</size_hpa2>
+        </memory>
+        <os_config>
+            <name desc="Specify the OS name of VM, currently it is not referenced by hypervisor code.">YOCTO</name>
+            <kern_type desc="kernel name">KERNEL_BZIMAGE</kern_type>
+            <kern_mod desc="The tag for kernel image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline.">Linux_bzImage</kern_mod>
+            <ramdisk_mod desc="The tag for ramdisk image which act as multiboot module, it must exactly match the module tag in GRUB multiboot cmdline." />
+            <bootargs desc="Specify kernel boot arguments">
+        rw rootwait root=/dev/sda3 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel log_buf_len=16M
+        consoleblank=0 tsc=reliable reboot=acpi
+        </bootargs>
+        </os_config>
+        <legacy_vuart id="0">
+            <type configurable="0" desc="vCOM1 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART0 (A.K.A COM1) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM1_BASE</base>
+            <irq configurable="0" desc="vCOM1 irq">COM1_IRQ</irq>
+        </legacy_vuart>
+        <legacy_vuart id="1">
+            <type configurable="0" desc="vCOM2 type">VUART_LEGACY_PIO</type>
+            <base desc="vUART1 (A.K.A COM2) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">COM2_BASE</base>
+            <irq configurable="0" desc="vCOM2 irq">COM2_IRQ</irq>
+            <target_vm_id desc="COM2 is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">0</target_vm_id>
+            <target_uart_id configurable="0" desc="target vUART ID that vCOM2 connect to">1</target_uart_id>
+        </legacy_vuart>
+        <console_vuart id="0">
+            <base desc="Console vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+        </console_vuart>
+        <communication_vuart id="1">
+            <base desc="Communicatin vuart (PCI based) enabling switch. Enable by exposing its base address, disable by returning invalid base address.">INVALID_PCI_BASE</base>
+            <target_vm_id desc="This vuart is used for VM communications. When it is enabled, please specify which target VM that current VM connect to.">1</target_vm_id>
+            <target_uart_id desc="target vUART ID that this vuart connects to">1</target_uart_id>
+        </communication_vuart>
+        <pci_devs desc="pci devices list">
+            <pci_dev desc="pci device" />
+            <pci_dev desc="pci device" />
+        </pci_devs>
+        <mmio_resources desc="mmio devices list to passthrough">
+            <TPM2 desc="TPM2 device">n</TPM2>
+        </mmio_resources>
+    </vm>
+</acrn-config>