mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-22 05:30:24 +00:00
HV: use the cached pci device info for sharing mode
Tracked-On: #2431 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Reviewed-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
dongshen
ACRN System Integration
parent
e0f9d14011
commit
983b717a61
@ -33,6 +33,7 @@
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static inline bool msicap_access(const struct pci_vdev *vdev, uint32_t offset)
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{
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bool ret;
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if (vdev->msi.capoff == 0U) {
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ret = 0;
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} else {
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@ -83,7 +84,8 @@ static int32_t vmsi_remap(const struct pci_vdev *vdev, bool enable)
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/* Update MSI Capability structure to physical device */
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_ADDR, 0x4U, (uint32_t)info.pmsi_addr.full);
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if ((msgctrl & PCIM_MSICTRL_64BIT) != 0U) {
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_ADDR_HIGH, 0x4U, (uint32_t)(info.pmsi_addr.full >> 32U));
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_ADDR_HIGH, 0x4U,
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(uint32_t)(info.pmsi_addr.full >> 32U));
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_DATA_64BIT, 0x2U, (uint16_t)info.pmsi_data.full);
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} else {
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_DATA, 0x2U, (uint16_t)info.pmsi_data.full);
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@ -166,68 +168,53 @@ static const struct pci_vdev_ops pci_ops_vdev_msi = {
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.cfgread = vmsi_cfgread,
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};
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/* Read a uint32_t from buffer (little endian) */
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static uint32_t buf_read32(const uint8_t buf[])
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{
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return buf[0] | ((uint32_t)buf[1] << 8U) | ((uint32_t)buf[2] << 16U) | ((uint32_t)buf[3] << 24U);
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}
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/* Write a uint32_t to buffer (little endian) */
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static void buf_write32(uint8_t buf[], uint32_t val)
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{
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buf[0] = (uint8_t)(val & 0xFFU);
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buf[1] = (uint8_t)((val >> 8U) & 0xFFU);
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buf[2] = (uint8_t)((val >> 16U) & 0xFFU);
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buf[3] = (uint8_t)((val >> 24U) & 0xFFU);
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}
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void populate_msi_struct(struct pci_vdev *vdev)
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{
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uint8_t ptr, cap;
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uint32_t msgctrl;
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uint32_t len, bytes, offset, val;
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union pci_bdf pbdf = vdev->pdev.bdf;
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struct pci_pdev *pdev = &vdev->pdev;
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uint32_t val;
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/* Has new Capabilities list? */
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if ((pci_pdev_read_cfg(pbdf, PCIR_STATUS, 2U) & PCIM_STATUS_CAPPRESENT) != 0U) {
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ptr = (uint8_t)pci_pdev_read_cfg(pbdf, PCIR_CAP_PTR, 1U);
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while ((ptr != 0U) && (ptr != 0xFFU)) {
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cap = (uint8_t)pci_pdev_read_cfg(pbdf, ptr + PCICAP_ID, 1U);
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/* Ignore all other Capability IDs for now */
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if ((cap == PCIY_MSI) || (cap == PCIY_MSIX)) {
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offset = ptr;
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if (cap == PCIY_MSI) {
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vdev->msi.capoff = offset;
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msgctrl = pci_pdev_read_cfg(pbdf, offset + PCIR_MSI_CTRL, 2U);
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/*
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* Ignore the 'mask' and 'pending' bits in the MSI capability
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* (msgctrl & PCIM_MSICTRL_VECTOR).
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* We'll let the guest manipulate them directly.
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*/
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len = ((msgctrl & PCIM_MSICTRL_64BIT) != 0U) ? 14U : 10U;
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vdev->msi.caplen = len;
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/* Copy MSI/MSI-X capability struct into virtual device */
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if (pdev->msi.capoff != 0U) {
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vdev->msi.capoff = pdev->msi.capoff;
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vdev->msi.caplen = pdev->msi.caplen;
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/* Assign MSI handler for configuration read and write */
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add_vdev_handler(vdev, &pci_ops_vdev_msi);
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} else {
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vdev->msix.capoff = offset;
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vdev->msix.caplen = MSIX_CAPLEN;
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len = vdev->msix.caplen;
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(void)memcpy_s((void *)&vdev->cfgdata.data_8[pdev->msi.capoff], pdev->msi.caplen,
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(void *)&pdev->msi.cap[0U], pdev->msi.caplen);
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val = buf_read32(&pdev->msi.cap[0U]);
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val &= ~((uint32_t)PCIM_MSICTRL_MMC_MASK << 16U);
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val &= ~((uint32_t)PCIM_MSICTRL_MME_MASK << 16U);
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buf_write32(&vdev->cfgdata.data_8[pdev->msi.capoff], val);
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}
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if (pdev->msix.capoff != 0U) {
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vdev->msix.capoff = pdev->msix.capoff;
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vdev->msix.caplen = pdev->msix.caplen;
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/* Assign MSI-X handler for configuration read and write */
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add_vdev_handler(vdev, &pci_ops_vdev_msix);
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}
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/* Copy MSI/MSI-X capability struct into virtual device */
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while (len > 0U) {
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bytes = (len >= 4U) ? 4U : len;
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val = pci_pdev_read_cfg(pbdf, offset, bytes);
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if ((cap == PCIY_MSI) && (offset == vdev->msi.capoff)) {
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/*
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* Don't support multiple vector for now,
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* Force Multiple Message Enable and Multiple Message
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* Capable to 0
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*/
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val &= ~((uint32_t)PCIM_MSICTRL_MMC_MASK << 16U);
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val &= ~((uint32_t)PCIM_MSICTRL_MME_MASK << 16U);
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}
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pci_vdev_write_cfg(vdev, offset, bytes, val);
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len -= bytes;
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offset += bytes;
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}
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}
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ptr = (uint8_t)pci_pdev_read_cfg(pbdf, ptr + PCICAP_NEXTPTR, 1U);
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}
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(void)memcpy_s((void *)&vdev->cfgdata.data_8[pdev->msix.capoff], pdev->msix.caplen,
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(void *)&pdev->msix.cap[0U], pdev->msix.caplen);
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}
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}
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@ -189,7 +189,6 @@ static int32_t vmsix_cfgwrite(struct pci_vdev *vdev, uint32_t offset, uint32_t b
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pci_pdev_write_cfg(vdev->pdev.bdf, offset, 2U, val);
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}
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}
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ret = 0;
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} else {
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ret = -ENODEV;
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@ -230,6 +229,7 @@ static void vmsix_table_rw(struct pci_vdev *vdev, struct mmio_request *mmio, uin
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*/
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if (entry_offset < offsetof(struct msix_table_entry, data)) {
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uint64_t qword_mask = ~0UL;
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if (mmio->size == 4U) {
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qword_mask = (entry_offset == 0U) ?
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0x00000000FFFFFFFFUL : 0xFFFFFFFF00000000UL;
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@ -311,67 +311,18 @@ static int32_t vmsix_table_mmio_access_handler(struct io_request *io_req, void *
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return ret;
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}
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static void decode_msix_table_bar(struct pci_vdev *vdev)
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{
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uint32_t bir = vdev->msix.table_bar;
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union pci_bdf pbdf = vdev->pdev.bdf;
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uint64_t base, size;
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uint32_t bar_lo, bar_hi, val32;
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bar_lo = pci_pdev_read_cfg(pbdf, pci_bar_offset(bir), 4U);
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if ((bar_lo & PCIM_BAR_SPACE) != PCIM_BAR_IO_SPACE) {
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/* Get the base address */
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base = (uint64_t)bar_lo & PCIM_BAR_MEM_BASE;
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if ((bar_lo & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64) {
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bar_hi = pci_pdev_read_cfg(pbdf, pci_bar_offset(bir + 1U), 4U);
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base |= ((uint64_t)bar_hi << 32U);
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}
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vdev->msix.mmio_hva = (uint64_t)hpa2hva(base);
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vdev->msix.mmio_gpa = sos_vm_hpa2gpa(base);
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/* Sizing the BAR */
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size = 0U;
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if (((bar_lo & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64) && (bir < (PCI_BAR_COUNT - 1U))) {
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir + 1U), 4U, ~0U);
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size = (uint64_t)pci_pdev_read_cfg(pbdf, pci_bar_offset(bir + 1U), 4U);
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size <<= 32U;
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}
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir), 4U, ~0U);
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val32 = pci_pdev_read_cfg(pbdf, pci_bar_offset(bir), 4U);
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size |= ((uint64_t)val32 & PCIM_BAR_MEM_BASE);
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vdev->msix.mmio_size = size & ~(size - 1U);
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/* Restore the BAR */
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir), 4U, bar_lo);
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if ((bar_lo & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64) {
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir + 1U), 4U, bar_hi);
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}
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} else {
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/* I/O bar, should never happen */
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pr_err("PCI device (%x) has MSI-X Table at IO BAR", vdev->vbdf.value);
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}
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}
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static int32_t vmsix_init(struct pci_vdev *vdev)
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{
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uint32_t msgctrl;
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uint32_t table_info, i;
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uint32_t i;
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uint64_t addr_hi, addr_lo;
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struct pci_msix *msix = &vdev->msix;
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struct pci_pdev *pdev = &vdev->pdev;
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struct pci_bar *bar;
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int32_t ret;
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msgctrl = pci_pdev_read_cfg(vdev->pdev.bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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/* Read Table Offset and Table BIR */
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table_info = pci_pdev_read_cfg(vdev->pdev.bdf, msix->capoff + PCIR_MSIX_TABLE, 4U);
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msix->table_bar = table_info & PCIM_MSIX_BIR_MASK;
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msix->table_offset = table_info & ~PCIM_MSIX_BIR_MASK;
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msix->table_count = (msgctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1U;
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msix->table_bar = pdev->msix.table_bar;
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msix->table_offset = pdev->msix.table_offset;
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msix->table_count = pdev->msix.table_count;
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if (msix->table_bar < (PCI_BAR_COUNT - 1U)) {
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/* Mask all table entries */
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@ -381,7 +332,12 @@ static int32_t vmsix_init(struct pci_vdev *vdev)
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msix->tables[i].data = 0U;
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}
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decode_msix_table_bar(vdev);
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bar = &pdev->bar[msix->table_bar];
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if (bar != NULL) {
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vdev->msix.mmio_hva = (uint64_t)hpa2hva(bar->base);
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vdev->msix.mmio_gpa = sos_vm_hpa2gpa(bar->base);
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vdev->msix.mmio_size = bar->size;
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}
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if (msix->mmio_gpa != 0U) {
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/*
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@ -102,31 +102,32 @@ static void sharing_mode_cfgwrite(__unused struct acrn_vpci *vpci, union pci_bdf
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}
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}
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static struct pci_vdev *alloc_pci_vdev(const struct acrn_vm *vm, union pci_bdf bdf)
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static struct pci_vdev *alloc_pci_vdev(const struct acrn_vm *vm, const struct pci_pdev *pdev_ref)
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{
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struct pci_vdev *vdev;
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struct pci_vdev *vdev = NULL;
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if (num_pci_vdev < CONFIG_MAX_PCI_DEV_NUM) {
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vdev = &sharing_mode_vdev_array[num_pci_vdev];
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num_pci_vdev++;
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/* vbdf equals to pbdf otherwise remapped */
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vdev->vbdf = bdf;
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if ((vm != NULL) && (vdev != NULL) && (pdev_ref != NULL)) {
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vdev->vpci = &vm->vpci;
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vdev->pdev.bdf = bdf;
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} else {
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vdev = NULL;
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/* vbdf equals to pbdf otherwise remapped */
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vdev->vbdf = pdev_ref->bdf;
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(void)memcpy_s((void *)&vdev->pdev, sizeof(struct pci_pdev),
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(const void *)pdev_ref, sizeof(struct pci_pdev));
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}
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}
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return vdev;
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}
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static void enumerate_pci_dev(uint16_t pbdf, const void *cb_data)
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static void init_vdev_for_pdev(const struct pci_pdev *pdev, const void *cb_data)
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{
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const struct acrn_vm *vm = (const struct acrn_vm *)cb_data;
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struct pci_vdev *vdev;
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vdev = alloc_pci_vdev(vm, (union pci_bdf)pbdf);
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vdev = alloc_pci_vdev(vm, pdev);
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if (vdev != NULL) {
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populate_msi_struct(vdev);
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}
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@ -145,12 +146,8 @@ static int32_t sharing_mode_vpci_init(const struct acrn_vm *vm)
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if (!is_sos_vm(vm)) {
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ret = -ENODEV;
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} else {
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/* Initialize PCI vdev array */
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num_pci_vdev = 0U;
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(void)memset((void *)sharing_mode_vdev_array, 0U, sizeof(sharing_mode_vdev_array));
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/* build up vdev array for sos_vm */
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pci_scan_bus(enumerate_pci_dev, vm);
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/* Build up vdev array for sos_vm */
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pci_pdev_foreach(init_vdev_for_pdev, vm);
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for (i = 0U; i < num_pci_vdev; i++) {
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vdev = &sharing_mode_vdev_array[i];
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@ -36,6 +36,8 @@ static spinlock_t pci_device_lock;
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static uint32_t num_pci_pdev;
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static struct pci_pdev pci_pdev_array[CONFIG_MAX_PCI_DEV_NUM];
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static void init_pdev(uint16_t pbdf);
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static uint32_t pci_pdev_calc_address(union pci_bdf bdf, uint32_t offset)
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{
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@ -122,7 +124,7 @@ void enable_disable_pci_intx(union pci_bdf bdf, bool enable)
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#define BUS_SCAN_SKIP 0U
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#define BUS_SCAN_PENDING 1U
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#define BUS_SCAN_COMPLETE 2U
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void pci_scan_bus(pci_enumeration_cb cb_func, const void *cb_data)
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void init_pci_pdev_list(void)
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{
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union pci_bdf pbdf;
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uint8_t hdr_type, secondary_bus, dev, func;
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@ -163,9 +165,7 @@ void pci_scan_bus(pci_enumeration_cb cb_func, const void *cb_data)
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continue;
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}
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if (cb_func != NULL) {
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cb_func(pbdf.value, cb_data);
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}
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init_pdev(pbdf.value);
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hdr_type = (uint8_t)pci_pdev_read_cfg(pbdf, PCIR_HDRTYPE, 1U);
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if ((hdr_type & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) {
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@ -380,22 +380,24 @@ static void fill_pdev(uint16_t pbdf, struct pci_pdev *pdev)
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}
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}
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static void init_pdev(uint16_t pbdf, __unused const void *cb_data)
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static void init_pdev(uint16_t pbdf)
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{
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static struct pci_pdev *curpdev = NULL;
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if (num_pci_pdev < CONFIG_MAX_PCI_DEV_NUM) {
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curpdev = &pci_pdev_array[num_pci_pdev];
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fill_pdev(pbdf, &pci_pdev_array[num_pci_pdev]);
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num_pci_pdev++;
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fill_pdev(pbdf, curpdev);
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} else {
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pr_err("%s, failed to alloc pci_pdev!\n", __func__);
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}
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}
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void init_pci_pdev_list(void)
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void pci_pdev_foreach(pci_pdev_enumeration_cb cb_func, const void *ctx)
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{
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/* Build up pdev array */
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pci_scan_bus(init_pdev, NULL);
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uint32_t idx;
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for (idx = 0U; idx < num_pci_pdev; idx++) {
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if (cb_func != NULL) {
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cb_func(&pci_pdev_array[idx], ctx);
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}
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}
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}
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@ -179,8 +179,7 @@ struct pci_pdev {
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struct pci_msix_cap msix;
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};
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typedef void (*pci_enumeration_cb)(uint16_t pbdf, const void *data);
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typedef void (*pci_pdev_enumeration_cb)(const struct pci_pdev *pdev, const void *data);
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static inline uint32_t pci_bar_offset(uint32_t idx)
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{
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@ -225,7 +224,7 @@ uint32_t pci_pdev_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes);
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void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
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void enable_disable_pci_intx(union pci_bdf bdf, bool enable);
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void pci_scan_bus(pci_enumeration_cb cb, const void *cb_data);
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void pci_pdev_foreach(pci_pdev_enumeration_cb cb, const void *ctx);
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void init_pci_pdev_list(void);
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