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https://github.com/projectacrn/acrn-hypervisor.git
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HV: scan all physical PCI devices and store all needed info in array
Tracked-On: #2431 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Signed-off-by: Victor Sun <victor.sun@intel.com> Reviewed-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
dongshen
ACRN System Integration
parent
65f9370d76
commit
e0f9d14011
@ -195,6 +195,7 @@ void init_cpu_post(uint16_t pcpu_id)
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timer_init();
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setup_notification();
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setup_posted_intr_notification();
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init_pci_pdev_list();
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/* Start all secondary cores */
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startup_paddr = prepare_trampoline();
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@ -1,4 +1,6 @@
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/*
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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@ -30,10 +32,10 @@
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#include <hypervisor.h>
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#include <pci.h>
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static spinlock_t pci_device_lock = {
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.head = 0U,
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.tail = 0U
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};
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static spinlock_t pci_device_lock;
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static uint32_t num_pci_pdev;
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static struct pci_pdev pci_pdev_array[CONFIG_MAX_PCI_DEV_NUM];
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static uint32_t pci_pdev_calc_address(union pci_bdf bdf, uint32_t offset)
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{
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@ -145,7 +147,7 @@ void pci_scan_bus(pci_enumeration_cb cb_func, const void *cb_data)
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pbdf.bits.f = func;
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val = pci_pdev_read_cfg(pbdf, PCIR_VENDOR, 4U);
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if ((val == 0xFFFFFFFFU) || (val == 0x0U)) {
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if ((val == 0xFFFFFFFFU) || (val == 0U) || (val == 0xFFFF0000U) || (val == 0xFFFFU)) {
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/* If function 0 is not implemented, skip to next device */
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if (func == 0U) {
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break;
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@ -181,3 +183,219 @@ void pci_scan_bus(pci_enumeration_cb cb_func, const void *cb_data)
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}
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}
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}
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static uint8_t pci_pdev_get_num_bars(uint8_t hdr_type)
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{
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uint8_t num_bars = (uint8_t)0U;
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switch (hdr_type & PCIM_HDRTYPE) {
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case PCIM_HDRTYPE_NORMAL:
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num_bars = (uint8_t)6U;
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break;
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case PCIM_HDRTYPE_BRIDGE:
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num_bars = (uint8_t)2U;
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break;
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case PCIM_HDRTYPE_CARDBUS:
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num_bars = (uint8_t)1U;
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break;
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default:
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/*no actions are required for other cases.*/
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break;
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}
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return num_bars;
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}
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static enum pci_bar_type pci_pdev_read_bar_type(union pci_bdf bdf, uint8_t idx)
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{
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uint32_t bar;
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enum pci_bar_type type = PCIBAR_NONE;
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bar = pci_pdev_read_cfg(bdf, pci_bar_offset(idx), 4U);
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if ((bar & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) {
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type = PCIBAR_IO_SPACE;
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} else {
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switch (bar & PCIM_BAR_MEM_TYPE) {
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case PCIM_BAR_MEM_32:
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case PCIM_BAR_MEM_1MB:
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type = PCIBAR_MEM32;
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break;
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case PCIM_BAR_MEM_64:
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type = PCIBAR_MEM64;
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break;
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default:
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/*no actions are required for other cases.*/
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break;
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}
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}
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return type;
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}
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static uint8_t pci_pdev_read_bar(union pci_bdf bdf, uint8_t idx, struct pci_bar *bar)
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{
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uint64_t base, size;
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enum pci_bar_type type;
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uint32_t bar_lo, bar_hi, val32;
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uint32_t bar_base_mask;
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base = 0UL;
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size = 0UL;
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type = pci_pdev_read_bar_type(bdf, idx);
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if (type != PCIBAR_NONE) {
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if (type == PCIBAR_IO_SPACE) {
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bar_base_mask = ~0x03U;
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} else {
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bar_base_mask = ~0x0fU;
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}
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bar_lo = pci_pdev_read_cfg(bdf, pci_bar_offset(idx), 4U);
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/* Get the base address */
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base = (uint64_t)bar_lo & bar_base_mask;
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if (base != 0UL) {
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if (type == PCIBAR_MEM64) {
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bar_hi = pci_pdev_read_cfg(bdf, pci_bar_offset(idx + 1U), 4U);
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base |= ((uint64_t)bar_hi << 32U);
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}
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/* Sizing the BAR */
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size = 0UL;
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if ((type == PCIBAR_MEM64) && (idx < (PCI_BAR_COUNT - 1U))) {
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pci_pdev_write_cfg(bdf, pci_bar_offset(idx + 1U), 4U, ~0U);
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size = (uint64_t)pci_pdev_read_cfg(bdf, pci_bar_offset(idx + 1U), 4U);
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size <<= 32U;
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}
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pci_pdev_write_cfg(bdf, pci_bar_offset(idx), 4U, ~0U);
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val32 = pci_pdev_read_cfg(bdf, pci_bar_offset(idx), 4U);
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size |= ((uint64_t)val32 & bar_base_mask);
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if (size != 0UL) {
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size = size & ~(size - 1U);
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}
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/* Restore the BAR */
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pci_pdev_write_cfg(bdf, pci_bar_offset(idx), 4U, bar_lo);
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if (type == PCIBAR_MEM64) {
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pci_pdev_write_cfg(bdf, pci_bar_offset(idx + 1U), 4U, bar_hi);
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}
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}
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}
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bar->base = base;
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bar->size = size;
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bar->type = type;
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return (type == PCIBAR_MEM64)?2U:1U;
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}
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/*
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* @pre nr_bars <= PCI_BAR_COUNT
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*/
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static void pci_pdev_read_bars(union pci_bdf bdf, uint8_t nr_bars, struct pci_bar *bar)
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{
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uint8_t idx = 0U;
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while (idx < nr_bars) {
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idx += pci_pdev_read_bar(bdf, idx, &bar[idx]);
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}
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}
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static void pci_read_cap(struct pci_pdev *pdev)
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{
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uint8_t ptr, cap;
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uint32_t msgctrl;
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uint32_t len, offset, idx;
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uint32_t table_info;
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ptr = (uint8_t)pci_pdev_read_cfg(pdev->bdf, PCIR_CAP_PTR, 1U);
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while ((ptr != 0U) && (ptr != 0xFFU)) {
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cap = (uint8_t)pci_pdev_read_cfg(pdev->bdf, ptr + PCICAP_ID, 1U);
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/* Ignore all other Capability IDs for now */
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if ((cap == PCIY_MSI) || (cap == PCIY_MSIX)) {
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offset = ptr;
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if (cap == PCIY_MSI) {
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pdev->msi.capoff = offset;
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msgctrl = pci_pdev_read_cfg(pdev->bdf, offset + PCIR_MSI_CTRL, 2U);
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len = ((msgctrl & PCIM_MSICTRL_64BIT) != 0U) ? 14U : 10U;
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pdev->msi.caplen = len;
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/* Copy MSI capability struct into buffer */
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for (idx = 0U; idx < len; idx++) {
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pdev->msi.cap[idx] = (uint8_t)pci_pdev_read_cfg(pdev->bdf, offset + idx, 1U);
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}
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} else {
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pdev->msix.capoff = offset;
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pdev->msix.caplen = MSIX_CAPLEN;
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len = pdev->msix.caplen;
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msgctrl = pci_pdev_read_cfg(pdev->bdf, pdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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/* Read Table Offset and Table BIR */
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table_info = pci_pdev_read_cfg(pdev->bdf, pdev->msix.capoff + PCIR_MSIX_TABLE, 4U);
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pdev->msix.table_bar = (uint8_t)(table_info & PCIM_MSIX_BIR_MASK);
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pdev->msix.table_offset = table_info & ~PCIM_MSIX_BIR_MASK;
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pdev->msix.table_count = (msgctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1U;
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/* Copy MSIX capability struct into buffer */
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for (idx = 0U; idx < len; idx++) {
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pdev->msix.cap[idx] = (uint8_t)pci_pdev_read_cfg(pdev->bdf, offset + idx, 1U);
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}
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}
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}
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ptr = (uint8_t)pci_pdev_read_cfg(pdev->bdf, ptr + PCICAP_NEXTPTR, 1U);
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}
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}
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static void fill_pdev(uint16_t pbdf, struct pci_pdev *pdev)
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{
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uint8_t hdr_type;
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uint8_t nr_bars;
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pdev->bdf.value = pbdf;
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hdr_type = (uint8_t)pci_pdev_read_cfg(pdev->bdf, PCIR_HDRTYPE, 1U);
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nr_bars = pci_pdev_get_num_bars(hdr_type);
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pci_pdev_read_bars(pdev->bdf, nr_bars, &pdev->bar[0]);
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if ((pci_pdev_read_cfg(pdev->bdf, PCIR_STATUS, 2U) & PCIM_STATUS_CAPPRESENT) != 0U) {
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pci_read_cap(pdev);
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}
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}
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static void init_pdev(uint16_t pbdf, __unused const void *cb_data)
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{
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static struct pci_pdev *curpdev = NULL;
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if (num_pci_pdev < CONFIG_MAX_PCI_DEV_NUM) {
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curpdev = &pci_pdev_array[num_pci_pdev];
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num_pci_pdev++;
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fill_pdev(pbdf, curpdev);
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} else {
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pr_err("%s, failed to alloc pci_pdev!\n", __func__);
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}
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}
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void init_pci_pdev_list(void)
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{
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/* Build up pdev array */
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pci_scan_bus(init_pdev, NULL);
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}
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@ -1,4 +1,5 @@
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/*-
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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@ -59,6 +60,8 @@
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#define PCIR_VENDOR 0x00U
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#define PCIR_DEVICE 0x02U
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#define PCIR_COMMAND 0x04U
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#define PCIM_CMD_PORTEN 0x01U
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#define PCIM_CMD_MEMEN 0x02U
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#define PCIM_CMD_INTxDIS 0x400U
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#define PCIR_STATUS 0x06U
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#define PCIM_STATUS_CAPPRESENT 0x0010U
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@ -69,6 +72,7 @@
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#define PCIM_HDRTYPE 0x7FU
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#define PCIM_HDRTYPE_NORMAL 0x00U
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#define PCIM_HDRTYPE_BRIDGE 0x01U
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#define PCIM_HDRTYPE_CARDBUS 0x02U
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#define PCIM_MFDEV 0x80U
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#define PCIR_BARS 0x10U
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#define PCIM_BAR_SPACE 0x01U
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@ -120,6 +124,7 @@
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#define PCIM_MSIX_BIR_MASK 0x7U
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#define PCIM_MSIX_VCTRL_MASK 0x1U
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#define MSI_MAX_CAPLEN 14U
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#define MSIX_CAPLEN 12U
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#define MSIX_TABLE_ENTRY_SIZE 16U
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@ -134,6 +139,7 @@ union pci_bdf {
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enum pci_bar_type {
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PCIBAR_NONE = 0,
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PCIBAR_IO_SPACE,
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PCIBAR_MEM32,
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PCIBAR_MEM64,
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};
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@ -144,12 +150,33 @@ struct pci_bar {
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enum pci_bar_type type;
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};
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/* Basic MSI capability info */
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struct pci_msi_cap {
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uint32_t capoff;
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uint32_t caplen;
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uint8_t cap[MSI_MAX_CAPLEN];
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};
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/* Basic MSIX capability info */
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struct pci_msix_cap {
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uint32_t capoff;
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uint32_t caplen;
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uint8_t table_bar;
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uint32_t table_offset;
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uint32_t table_count;
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uint8_t cap[MSIX_CAPLEN];
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};
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struct pci_pdev {
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/* The bar info of the physical PCI device. */
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struct pci_bar bar[PCI_BAR_COUNT];
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/* The bus/device/function triple of the physical PCI device. */
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union pci_bdf bdf;
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struct pci_msi_cap msi;
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struct pci_msix_cap msix;
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};
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@ -199,5 +226,7 @@ void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint
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void enable_disable_pci_intx(union pci_bdf bdf, bool enable);
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void pci_scan_bus(pci_enumeration_cb cb, const void *cb_data);
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void init_pci_pdev_list(void);
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#endif /* PCI_H_ */
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