mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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board_inspector/acpiparser: enable parsing RTCT v2
This patch adds support to parse RTCT v2 using the refined board XML schema. The major changes include: - Add the RTCT v2 parser in the acpiparser module. The version of an RTCT is detected automatically to choose the right parser. - Extract software SRAM capabilities of caches into the board XML. - Move the logic that determines the software SRAM base address for the pre-launched VM to the static allocator of GPAs. - Generate software SRAM related macros into misc_cfg.h when necessary. Tracked-On: #6020 Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao
wenlingz
parent
c0fef0b1fb
commit
99f15a27c2
@ -3,7 +3,7 @@
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# SPDX-License-Identifier: BSD-3-Clause
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#
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import sys
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import sys, os
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from acpiparser.apic import APIC
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from acpiparser.asf import ASF
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@ -29,4 +29,11 @@ parse_asf = make_parser('ASF!')
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parse_dsdt = make_parser('DSDT')
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parse_dmar = make_parser('DMAR')
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parse_facp = make_parser('FACP')
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parse_rtct = make_parser('RTCT')
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def parse_rtct(path=None):
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if not path:
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path = f"/sys/firmware/acpi/tables/RTCT"
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if not os.path.exists(path):
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path = f"/sys/firmware/acpi/tables/PTCT"
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fn = getattr(sys.modules[f"acpiparser.rtct"], "RTCT")
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return fn(path)
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@ -9,14 +9,43 @@ import copy
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import lib.cdata as cdata
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from acpiparser._utils import TableHeader
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# Common structures
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class RTCTSubtable(cdata.Struct):
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_pack_ = 1
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_fields_ = [
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('size', ctypes.c_uint16),
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('subtable_size', ctypes.c_uint16),
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('format', ctypes.c_uint16),
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('type', ctypes.c_uint32),
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]
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ACPI_RTCT_TYPE_COMPATIBILITY = 0
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class RTCTSubtableCompatibility(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('rtct_version_major', ctypes.c_uint32),
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('rtct_version_minor', ctypes.c_uint32),
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('rtcd_version_major', ctypes.c_uint32),
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('rtcd_version_minor', ctypes.c_uint32),
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]
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def RTCTSubtableUnknown_factory(data_len):
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class RTCTSubtableUnknown(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('data', ctypes.c_uint8 * data_len),
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]
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return RTCTSubtableUnknown
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# RTCT v1
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ACPI_RTCT_V1_TYPE_RTCM_BINARY = 2
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ACPI_RTCT_V1_TYPE_WRC_L3Waymasks = 3
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ACPI_RTCT_V1_TYPE_GT_L3Waymasks = 4
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ACPI_RTCT_V1_TYPE_SoftwareSRAM = 5
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ACPI_RTCT_V1_TYPE_Memory_Hierarchy_Latency = 9
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class RTCTSubtableRTCMBinary(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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@ -28,7 +57,7 @@ def RTCTSubtableWRCL3Waymasks_factory(data_len):
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class RTCTSubtableWRCL3Waymasks(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('waskmask', ctypes.c_uint32 * (data_len // 4)),
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('waymask', ctypes.c_uint32 * (data_len // 4)),
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]
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return RTCTSubtableWRCL3Waymasks
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@ -36,12 +65,12 @@ def RTCTSubtableGTL3Waymasks_factory(data_len):
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class RTCTSubtableGTL3Waymasks(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('waskmask', ctypes.c_uint32 * (data_len // 4)),
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('waymask', ctypes.c_uint32 * (data_len // 4)),
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]
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return RTCTSubtableGTL3Waymasks
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def RTCTSubtableSoftwareSRAM_factory(data_len):
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class RTCTSubtableSoftwareSRAM(cdata.Struct):
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def RTCTSubtableSoftwareSRAM_v1_factory(data_len):
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class RTCTSubtableSoftwareSRAM_v1(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('cache_level', ctypes.c_uint32),
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@ -50,57 +79,186 @@ def RTCTSubtableSoftwareSRAM_factory(data_len):
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('size', ctypes.c_uint32),
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('apic_id_tbl', ctypes.c_uint32 * ((data_len - 20) // 4)),
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]
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return RTCTSubtableSoftwareSRAM
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return RTCTSubtableSoftwareSRAM_v1
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def RTCTSubtableMemoryHierarchyLatency_factory(data_len):
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class RTCTSubtableMemoryHierarchyLatency(cdata.Struct):
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def RTCTSubtableMemoryHierarchyLatency_v1_factory(data_len):
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class RTCTSubtableMemoryHierarchyLatency_v1(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('hierarchy', ctypes.c_uint32),
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('clock_cycles', ctypes.c_uint32),
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('apic_id_tbl', ctypes.c_uint32 * ((data_len - 8) // 4)),
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]
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return RTCTSubtableMemoryHierarchyLatency
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return RTCTSubtableMemoryHierarchyLatency_v1
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def RTCTSubtableUnknown_factory(data_len):
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class RTCTSubtableUnknown(cdata.Struct):
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# RTCT v2
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ACPI_RTCT_V2_TYPE_RTCD_Limits = 1
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ACPI_RTCT_V2_TYPE_CRL_Binary = 2
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ACPI_RTCT_V2_TYPE_IA_WayMasks = 3
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ACPI_RTCT_V2_TYPE_WRC_WayMasks = 4
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ACPI_RTCT_V2_TYPE_GT_WayMasks = 5
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ACPI_RTCT_V2_TYPE_SSRAM_WayMask = 6
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ACPI_RTCT_V2_TYPE_SoftwareSRAM = 7
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ACPI_RTCT_V2_TYPE_MemoryHierarchyLatency = 8
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ACPI_RTCT_V2_TYPE_ErrorLogAddress = 9
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class RTCTSubtableRTCDLimits(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('total_ia_l2_clos', ctypes.c_uint32),
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('total_ia_l3_clos', ctypes.c_uint32),
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('total_l2_instances', ctypes.c_uint32),
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('total_l3_instances', ctypes.c_uint32),
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('total_gt_clos', ctypes.c_uint32),
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('total_wrc_clos', ctypes.c_uint32),
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('max_tcc_streams', ctypes.c_uint32),
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('max_tcc_registers', ctypes.c_uint32),
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]
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def RTCTSubtableIAWayMasks_factory(data_len):
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class RTCTSubtableIAWayMasks(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('data', ctypes.c_uint8 * data_len),
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('level', ctypes.c_uint32),
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('cache_id', ctypes.c_uint32),
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('waymask', ctypes.c_uint32 * ((data_len - 8) // 4)),
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]
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return RTCTSubtableUnknown
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return RTCTSubtableIAWayMasks
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ACPI_RTCT_TYPE_RTCM_BINARY = 2
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ACPI_RTCT_TYPE_WRC_L3Waymasks = 3
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ACPI_RTCT_TYPE_GT_L3Waymasks = 4
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ACPI_RTCT_TYPE_SoftwareSRAM = 5
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ACPI_RTCT_TYPE_Memory_Hierarchy_Latency = 9
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class RTCTSubtableWRCWayMasks(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('level', ctypes.c_uint32),
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('cache_id', ctypes.c_uint32),
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('waymask', ctypes.c_uint32),
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]
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def rtct_subtable_list(addr, length):
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def RTCTSubtableGTWayMasks_factory(data_len):
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class RTCTSubtableGTWayMasks(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('level', ctypes.c_uint32),
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('cache_id', ctypes.c_uint32),
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('waymask', ctypes.c_uint32 * ((data_len - 8) // 4)),
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]
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return RTCTSubtableGTWayMasks
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class RTCTSubtableSSRAMWayMask(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('level', ctypes.c_uint32),
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('cache_id', ctypes.c_uint32),
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('waymask', ctypes.c_uint32),
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]
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def RTCTSubtableSoftwareSRAM_v2_factory(data_len):
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class RTCTSubtableSoftwareSRAM_v2(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('level', ctypes.c_uint32),
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('cache_id', ctypes.c_uint32),
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('base', ctypes.c_uint64),
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('size', ctypes.c_uint32),
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('shared', ctypes.c_uint32),
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]
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return RTCTSubtableSoftwareSRAM_v2
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def RTCTSubtableMemoryHierarchyLatency_v2_factory(data_len):
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class RTCTSubtableMemoryHierarchyLatency_v2(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('hierarchy', ctypes.c_uint32),
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('clock_cycles', ctypes.c_uint32),
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('cache_id', ctypes.c_uint32 * ((data_len - 8) // 4)),
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]
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return RTCTSubtableMemoryHierarchyLatency_v2
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class RTCTSubtableErrorLogAddress(cdata.Struct):
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_pack_ = 1
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_fields_ = copy.copy(RTCTSubtable._fields_) + [
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('address', ctypes.c_uint64),
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('size', ctypes.c_uint32),
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]
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# Parsers
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def rtct_version(addr, length):
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end = addr + length
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while addr < end:
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subtable = RTCTSubtable.from_address(addr)
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if subtable.type == ACPI_RTCT_TYPE_COMPATIBILITY:
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subtable = RTCTSubtableCompatibility.from_address(addr)
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return subtable.rtct_version_major
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addr += subtable.subtable_size
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# RTCT v1 does not have a compatibility entry
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return 1
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def rtct_v1_subtable_list(addr, length):
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end = addr + length
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field_list = list()
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subtable_num = 0
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while addr < end:
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subtable_num += 1
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subtable = RTCTSubtable.from_address(addr)
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data_len = subtable.size - ctypes.sizeof(RTCTSubtable)
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if subtable.type == ACPI_RTCT_TYPE_RTCM_BINARY:
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data_len = subtable.subtable_size - ctypes.sizeof(RTCTSubtable)
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if subtable.type == ACPI_RTCT_V1_TYPE_RTCM_BINARY:
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cls = RTCTSubtableRTCMBinary
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elif subtable.type == ACPI_RTCT_TYPE_WRC_L3Waymasks:
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elif subtable.type == ACPI_RTCT_V1_TYPE_WRC_L3Waymasks:
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cls = RTCTSubtableWRCL3Waymasks_factory(data_len)
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elif subtable.type == ACPI_RTCT_TYPE_GT_L3Waymasks:
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elif subtable.type == ACPI_RTCT_V1_TYPE_GT_L3Waymasks:
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cls = RTCTSubtableGTL3Waymasks_factory(data_len)
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elif subtable.type == ACPI_RTCT_TYPE_SoftwareSRAM:
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cls = RTCTSubtableSoftwareSRAM_factory(data_len)
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elif subtable.type == ACPI_RTCT_TYPE_Memory_Hierarchy_Latency:
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cls = RTCTSubtableMemoryHierarchyLatency_factory(data_len)
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elif subtable.type == ACPI_RTCT_V1_TYPE_SoftwareSRAM:
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cls = RTCTSubtableSoftwareSRAM_v1_factory(data_len)
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elif subtable.type == ACPI_RTCT_V1_TYPE_Memory_Hierarchy_Latency:
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cls = RTCTSubtableMemoryHierarchyLatency_v1_factory(data_len)
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else:
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cls = RTCTSubtableUnknown_factory(data_len)
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addr += subtable.size
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addr += subtable.subtable_size
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field_list.append( ('subtable{}'.format(subtable_num), cls) )
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return field_list
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def rtct_factory(field_list):
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def rtct_v2_subtable_list(addr, length):
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end = addr + length
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field_list = list()
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subtable_num = 0
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while addr < end:
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subtable_num += 1
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subtable = RTCTSubtable.from_address(addr)
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data_len = subtable.subtable_size - ctypes.sizeof(RTCTSubtable)
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if subtable.type == ACPI_RTCT_V2_TYPE_RTCD_Limits:
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cls = RTCTSubtableRTCDLimits
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elif subtable.type == ACPI_RTCT_V2_TYPE_CRL_Binary:
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cls = RTCTSubtableRTCMBinary
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elif subtable.type == ACPI_RTCT_V2_TYPE_IA_WayMasks:
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cls = RTCTSubtableIAWayMasks_factory(data_len)
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elif subtable.type == ACPI_RTCT_V2_TYPE_WRC_WayMasks:
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cls = RTCTSubtableWRCWayMasks
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elif subtable.type == ACPI_RTCT_V2_TYPE_GT_WayMasks:
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cls = RTCTSubtableGTWayMasks_factory(data_len)
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elif subtable.type == ACPI_RTCT_V2_TYPE_SSRAM_WayMask:
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cls = RTCTSubtableSSRAMWayMask
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elif subtable.type == ACPI_RTCT_V2_TYPE_SoftwareSRAM:
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cls = RTCTSubtableSoftwareSRAM_v2_factory(data_len)
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elif subtable.type == ACPI_RTCT_V2_TYPE_MemoryHierarchyLatency:
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cls = RTCTSubtableMemoryHierarchyLatency_v2_factory(data_len)
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elif subtable.type == ACPI_RTCT_V2_TYPE_ErrorLogAddress:
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cls = RTCTSubtableErrorLogAddress
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else:
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cls = RTCTSubtableUnknown_factory(data_len)
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addr += subtable.subtable_size
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field_list.append( ('subtable{}'.format(subtable_num), cls) )
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return field_list
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def rtct_version_and_subtable_list(addr, length):
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version = rtct_version(addr, length)
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if version == 1:
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return (version, rtct_v1_subtable_list(addr, length))
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else:
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return (version, rtct_v2_subtable_list(addr, length))
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def rtct_factory(field_list, version):
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class subtables(cdata.Struct):
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_pack_ = 1
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@ -117,14 +275,18 @@ def rtct_factory(field_list):
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('entries', subtables),
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]
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@property
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def version(self):
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return version
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return RTCT
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def RTCT(val):
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"""Create class based on decode of an RTCT table from filename."""
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base_length = ctypes.sizeof(rtct_factory(list()))
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base_length = ctypes.sizeof(rtct_factory(list(), 0))
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data = open(val, mode='rb').read()
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buf = ctypes.create_string_buffer(data, len(data))
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addr = ctypes.addressof(buf)
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hdr = TableHeader.from_address(addr)
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field_list = rtct_subtable_list(addr + base_length, hdr.length - base_length)
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return rtct_factory(field_list).from_buffer_copy(data)
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version, field_list = rtct_version_and_subtable_list(addr + base_length, hdr.length - base_length)
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return rtct_factory(field_list, version).from_buffer_copy(data)
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@ -8,6 +8,8 @@ import lxml.etree
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from extractors.helpers import add_child, get_node
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from cpuparser import parse_cpuid
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from acpiparser import parse_rtct
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import acpiparser.rtct
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def extract_topology(root_node, caches_node):
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threads = root_node.xpath("//processors//*[cpu_id]")
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@ -48,11 +50,11 @@ def extract_topology(root_node, caches_node):
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else:
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leaf_10 = None
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if leaf_10 is not None:
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cap = add_child(n, "capability", None, kind="cat")
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cap = add_child(n, "capability", None, id="CAT")
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add_child(cap, "capacity_mask_length", str(leaf_10.capacity_mask_length))
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add_child(cap, "clos_number", str(leaf_10.clos_number))
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if leaf_10.code_and_data_prioritization == 1:
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add_child(n, "capability", None, kind="cdp")
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add_child(n, "capability", None, id="CDP")
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add_child(get_node(n, "processors"), "processor", get_node(thread, "apic_id/text()"))
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@ -65,7 +67,36 @@ def extract_topology(root_node, caches_node):
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return (level, id, type)
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caches_node[:] = sorted(caches_node, key=getkey)
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def extract_tcc_capabilities(caches_node):
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try:
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rtct = parse_rtct()
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if rtct.version == 1:
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for entry in rtct.entries:
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if entry.type == acpiparser.rtct.ACPI_RTCT_V1_TYPE_SoftwareSRAM:
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cache_node = get_node(caches_node, f"cache[@level='{entry.cache_level}' and processors/processor='{hex(entry.apic_id_tbl[0])}']")
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if cache_node is None:
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logging.warning(f"Cannot find the level {entry.cache_level} cache of physical processor with apic ID {entry.apic_id_tbl[0]}")
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continue
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cap = add_child(cache_node, "capability", None, id="Software SRAM")
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add_child(cap, "start", "0x{:08x}".format(entry.base))
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add_child(cap, "end", "0x{:08x}".format(entry.base + entry.size - 1))
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add_child(cap, "size", str(entry.size))
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elif rtct.version == 2:
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for entry in rtct.entries:
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if entry.type == acpiparser.rtct.ACPI_RTCT_V2_TYPE_SoftwareSRAM:
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cache_node = get_node(caches_node, f"cache[@level='{entry.level}' and @id='{hex(entry.cache_id)}']")
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if cache_node is None:
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logging.warning(f"Cannot find the level {entry.level} cache with cache ID {entry.cache_id}")
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continue
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cap = add_child(cache_node, "capability", None, id="Software SRAM")
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add_child(cap, "start", "0x{:08x}".format(entry.base))
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add_child(cap, "end", "0x{:08x}".format(entry.base + entry.size - 1))
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add_child(cap, "size", str(entry.size))
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except FileNotFoundError:
|
||||
pass
|
||||
|
||||
def extract(board_etree):
|
||||
root_node = board_etree.getroot()
|
||||
caches_node = get_node(board_etree, "//caches")
|
||||
extract_topology(root_node, caches_node)
|
||||
extract_tcc_capabilities(caches_node)
|
||||
|
||||
@ -14,7 +14,6 @@ import acpi
|
||||
import clos
|
||||
import misc
|
||||
import parser_lib
|
||||
import rtct
|
||||
|
||||
OUTPUT = "./out/"
|
||||
PY_CACHE = "__pycache__"
|
||||
@ -135,9 +134,6 @@ if __name__ == '__main__':
|
||||
# Generate misc info
|
||||
misc.generate_info(BOARD_INFO)
|
||||
|
||||
# Generate pseudo RAM info
|
||||
rtct.generate_info(BOARD_INFO)
|
||||
|
||||
with open(BOARD_INFO, 'a+') as f:
|
||||
print("</acrn-config>", file=f)
|
||||
|
||||
|
||||
@ -1,43 +0,0 @@
|
||||
# Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
import os
|
||||
from acpiparser import parse_rtct
|
||||
import acpiparser.rtct
|
||||
import parser_lib
|
||||
|
||||
def dump_ssram(config):
|
||||
print("\t<RTCT>", file=config)
|
||||
|
||||
rtct = None
|
||||
if os.path.exists("/sys/firmware/acpi/tables/PTCT"):
|
||||
rtct = parse_rtct(path="/sys/firmware/acpi/tables/PTCT")
|
||||
elif os.path.exists("/sys/firmware/acpi/tables/RTCT"):
|
||||
rtct = parse_rtct(path="/sys/firmware/acpi/tables/RTCT")
|
||||
|
||||
if rtct:
|
||||
for entry in rtct.entries:
|
||||
if entry.type == acpiparser.rtct.ACPI_RTCT_TYPE_SoftwareSRAM:
|
||||
print("\t\t<SoftwareSRAM>", file=config)
|
||||
print("\t\t\t<cache_level>{}</cache_level>".format(entry.cache_level), file=config)
|
||||
print("\t\t\t<base>{}</base>".format(hex(entry.base)), file=config)
|
||||
print("\t\t\t<ways>{}</ways>".format(hex(entry.ways)), file=config)
|
||||
print("\t\t\t<size>{}</size>".format(hex(entry.size)), file=config)
|
||||
for apic_id in entry.apic_id_tbl:
|
||||
print("\t\t\t<apic_id>{}</apic_id>".format(hex(apic_id)), file=config)
|
||||
print("\t\t</SoftwareSRAM>", file=config)
|
||||
else:
|
||||
parser_lib.print_yel("No PTCT or RTCT found. The platform may not support pseudo RAM.")
|
||||
|
||||
print("\t</RTCT>", file=config)
|
||||
print("", file=config)
|
||||
|
||||
|
||||
def generate_info(board_info):
|
||||
"""Get system pseudo RAM information
|
||||
:param board_info: this is the file which stores the hardware board information
|
||||
"""
|
||||
with open(board_info, 'a+') as config:
|
||||
dump_ssram(config)
|
||||
@ -36,4 +36,20 @@ or little cores are assigned, but not both.</xs:documentation>
|
||||
</xs:annotation>
|
||||
</xs:assert>
|
||||
|
||||
<xs:assert test="hv//PSRAM_ENABLED = 'n' or empty(vm[vm_type='PRE_RT_VM']) or
|
||||
every $cap in caches/cache[@level=3]/capability[@id='Software SRAM'] satisfies
|
||||
(compare($cap/end, '0x80000000') < 0 or compare($cap/start, '0xf8000000') >= 0)">
|
||||
<xs:annotation acrn:severity="warning">
|
||||
<xs:documentation>The physical software SRAM region shall not overlap with pre-defined regions in guest.
|
||||
|
||||
When a pre-launched RT VM is enabled, the physical software SRAM is allocated to it at the same guest physical
|
||||
address. Thus it is assumed that the software SRAM region does not overlap with any pre-defined region in the
|
||||
pre-launched VM, such as the guest PCI hole which resides at 2G - 3.5G.
|
||||
|
||||
This error cannot be fixed by tweaking the configurations. Report to _GitHub:
|
||||
https://github.com/projectacrn/acrn-hypervisor/issues if you meet this.</xs:documentation>
|
||||
|
||||
</xs:annotation>
|
||||
</xs:assert>
|
||||
|
||||
</xs:schema>
|
||||
|
||||
31
misc/config_tools/static_allocators/gpa.py
Normal file
31
misc/config_tools/static_allocators/gpa.py
Normal file
@ -0,0 +1,31 @@
|
||||
#!/usr/bin/env python3
|
||||
#
|
||||
# Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
import sys, os
|
||||
sys.path.append(os.path.join(os.path.dirname(os.path.abspath(__file__)), '..', 'library'))
|
||||
import common
|
||||
|
||||
def allocate_ssram_region(board_etree, scenario_etree, allocation_etree):
|
||||
# Guest physical address of the SW SRAM allocated to a pre-launched VM
|
||||
enabled = common.get_node("//PSRAM_ENABLED/text()", scenario_etree)
|
||||
if enabled == "y":
|
||||
pre_rt_vms = common.get_node("//vm[vm_type ='PRE_RT_VM']", scenario_etree)
|
||||
if pre_rt_vms is not None:
|
||||
vm_id = pre_rt_vms.get("id")
|
||||
l3_sw_sram = board_etree.xpath("//cache[@level='3']/capability[@id='Software SRAM']")
|
||||
if l3_sw_sram:
|
||||
start = min(map(lambda x: int(x.find("start").text, 16), l3_sw_sram))
|
||||
end = max(map(lambda x: int(x.find("end").text, 16), l3_sw_sram))
|
||||
|
||||
allocation_vm_node = common.get_node(f"/acrn-config/vm[@id = '{vm_id}']", allocation_etree)
|
||||
if allocation_vm_node is None:
|
||||
allocation_vm_node = common.append_node("/acrn-config/vm", None, allocation_etree, id = vm_id)
|
||||
common.append_node("./ssram/start_gpa", hex(start), allocation_vm_node)
|
||||
common.append_node("./ssram/end_gpa", hex(end), allocation_vm_node)
|
||||
|
||||
def fn(board_etree, scenario_etree, allocation_etree):
|
||||
allocate_ssram_region(board_etree, scenario_etree, allocation_etree)
|
||||
@ -22,6 +22,8 @@
|
||||
|
||||
<xsl:apply-templates select="config-data/acrn-config" />
|
||||
|
||||
<xsl:apply-templates select="allocation-data//ssram" />
|
||||
|
||||
<xsl:value-of select="acrn:include-guard-end('MISC_CFG_H')" />
|
||||
</xsl:template>
|
||||
|
||||
@ -40,6 +42,12 @@
|
||||
<xsl:call-template name="vm_pt_intx_num" />
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="allocation-data//ssram">
|
||||
<xsl:value-of select="acrn:define('PRE_RTVM_SW_SRAM_ENABLED', 1, '')" />
|
||||
<xsl:value-of select="acrn:define('PRE_RTVM_SW_SRAM_BASE_GPA', start_gpa, 'UL')" />
|
||||
<xsl:value-of select="acrn:define('PRE_RTVM_SW_SRAM_END_GPA', end_gpa, 'UL')" />
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template name="sos_rootfs">
|
||||
<xsl:value-of select="acrn:define('SOS_ROOTFS', concat($quot, 'root=', vm/board_private/rootfs[text()], ' ', $quot), '')" />
|
||||
</xsl:template>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user