mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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mmu:create temporary page tables for guest at run time
Before this patch, guest temporary page tables were generated by hardcode at compile time, HV will copy this page tables to guest before guest launch. This patch creates temporary page tables at runtime for the range of 0~4G, and create page tables to cover new range(511G~511G+16M) with trusty requirement. Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Mingqiang Chi
Jack Ren
parent
4d0f26d0e1
commit
9aa9a77457
@ -162,36 +162,4 @@ cpu_secondary_pdt_addr:
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address = address + 0x200000
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.endr
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/*******************************************************************
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* GUEST initial 4G page table
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*
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* guest starts with long mode, HV needs to prepare Guest identity
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* mapped page table.
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*
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* guest page tables covers 4G size, with 2M page size.
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*
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* HV copy this page table (6 pages) to guest address
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* CPU_Boot_Page_Tables_Start_VM before executing guest instruction.
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*
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******************************************************************/
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.align CPU_PAGE_SIZE
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.global CPU_Boot_Page_Tables_Start_VM
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CPU_Boot_Page_Tables_Start_VM:
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.quad vm_cpu_pdpt_addr + (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
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.align CPU_PAGE_SIZE
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vm_cpu_pdpt_addr:
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address = 0
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.rept 4
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.quad vm_cpu_pdt_addr + address + (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
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address = address + CPU_PAGE_SIZE
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.endr
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.align CPU_PAGE_SIZE
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vm_cpu_pdt_addr:
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address = 0
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.rept 2048
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.quad address + (IA32E_PDPTE_PS_BIT | IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
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address = address + 0x200000
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.endr
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.end
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@ -41,21 +41,6 @@
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#define ACRN_DBG_EPT 6
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void *create_guest_paging(struct vm *vm)
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{
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void *hva_dest;
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void *hva_src;
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/* copy guest identity mapped 4G page table to guest */
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hva_dest = GPA2HVA(vm,
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(uint64_t)CPU_Boot_Page_Tables_Start_VM);
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hva_src = (void *)(_ld_cpu_secondary_reset_load
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+ (CPU_Boot_Page_Tables_Start_VM
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- _ld_cpu_secondary_reset_start));
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/* 2MB page size, need to copy 6 pages */
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memcpy_s(hva_dest, 6 * CPU_PAGE_SIZE, hva_src, 6 * CPU_PAGE_SIZE);
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return (void *)CPU_Boot_Page_Tables_Start_VM;
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}
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static uint64_t find_next_table(uint32_t table_offset, void *table_base)
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{
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@ -335,3 +335,132 @@ int prepare_vm0_memmap_and_e820(struct vm *vm)
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CONFIG_RAM_SIZE, MAP_UNMAP, 0);
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return 0;
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}
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/*******************************************************************
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* GUEST initial page table
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*
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* guest starts with long mode, HV needs to prepare Guest identity
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* mapped page table.
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* For SOS:
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* Guest page tables cover 0~4G space with 2M page size, will use
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* 6 pages memory for page tables.
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* For UOS(Trusty not enabled):
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* Guest page tables cover 0~4G space with 2M page size, will use
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* 6 pages memory for page tables.
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* For UOS(Trusty enabled):
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* Guest page tables cover 0~4G and trusy memory space with 2M page size,
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* will use 7 pages memory for page tables.
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* This API assume that the trusty memory is remapped to guest physical address
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* of 511G to 511G + 16MB
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*
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* FIXME: here using hard code GUEST_INIT_PAGE_TABLE_START as guest init page
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* table gpa start, and it will occupy at most GUEST_INIT_PT_PAGE_NUM pages.
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* Some check here:
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* - guest page table space should not override cpu_secondary_reset code area
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* (it's a little tricky here, as under current identical mapping, HV & SOS
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* share same memory under 1M; under uefi boot mode, the defered AP startup
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* need cpu_secondary_reset code area which reserved by uefi stub keep there
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* no change even after SOS startup)
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* - guest page table space should not override possible RSDP fix segment
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*
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* Anyway, it's a tmp solution, the init page tables should be totally removed
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* after guest realmode/32bit no paging mode got supported.
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******************************************************************/
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#define GUEST_INIT_PAGE_TABLE_SKIP_SIZE 0x8000UL
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#define GUEST_INIT_PAGE_TABLE_START (CONFIG_LOW_RAM_START + \
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GUEST_INIT_PAGE_TABLE_SKIP_SIZE)
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#define GUEST_INIT_PT_PAGE_NUM 7
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#define RSDP_F_ADDR 0xE0000
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uint64_t create_guest_initial_paging(struct vm *vm)
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{
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uint64_t i = 0;
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uint64_t entry = 0;
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uint64_t entry_num = 0;
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uint64_t pdpt_base_paddr = 0;
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uint64_t pd_base_paddr = 0;
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uint64_t table_present = 0;
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uint64_t table_offset = 0;
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void *addr = NULL;
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void *pml4_addr = GPA2HVA(vm, GUEST_INIT_PAGE_TABLE_START);
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_Static_assert((GUEST_INIT_PAGE_TABLE_START + 7 * PAGE_SIZE_4K) <
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RSDP_F_ADDR, "RSDP fix segment could be override");
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if (GUEST_INIT_PAGE_TABLE_SKIP_SIZE <
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(unsigned long)&_ld_cpu_secondary_reset_size) {
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panic("guest init PTs override cpu_secondary_reset code");
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}
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/* Using continuous memory for guest page tables, the total 4K page
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* number for it(without trusty) is GUEST_INIT_PT_PAGE_NUM-1.
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* here make sure they are init as 0 (page entry no present)
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*/
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memset(pml4_addr, 0, PAGE_SIZE_4K * GUEST_INIT_PT_PAGE_NUM-1);
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/* Write PML4E */
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table_present = (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT);
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/* PML4 used 1 page, skip it to fetch PDPT */
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pdpt_base_paddr = GUEST_INIT_PAGE_TABLE_START + PAGE_SIZE_4K;
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entry = pdpt_base_paddr | table_present;
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MEM_WRITE64(pml4_addr, entry);
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/* Write PDPTE, PDPT used 1 page, skip it to fetch PD */
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pd_base_paddr = pdpt_base_paddr + PAGE_SIZE_4K;
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addr = pml4_addr + PAGE_SIZE_4K;
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/* Guest page tables cover 0~4G space with 2M page size */
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for (i = 0; i < 4; i++) {
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entry = ((pd_base_paddr + (i * PAGE_SIZE_4K))
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| table_present);
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MEM_WRITE64(addr, entry);
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addr += IA32E_COMM_ENTRY_SIZE;
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}
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/* Write PDE, PT used 4 pages */
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table_present = (IA32E_PDPTE_PS_BIT
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| IA32E_COMM_P_BIT
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| IA32E_COMM_RW_BIT);
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/* Totally 2048(512*4) entries with 2M page size for 0~4G*/
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entry_num = IA32E_NUM_ENTRIES * 4;
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addr = pml4_addr + 2 * PAGE_SIZE_4K;
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for (i = 0; i < entry_num; i++) {
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entry = (i * (1 << MMU_PDE_PAGE_SHIFT)) | table_present;
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MEM_WRITE64(addr, entry);
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addr += IA32E_COMM_ENTRY_SIZE;
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}
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/* For UOS, if trusty is enabled,
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* need to setup tempory page table for trusty
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* FIXME: this is a tempory solution for trusty enabling,
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* the final solution is that vSBL will setup guest page tables
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*/
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if (vm->sworld_control.sworld_enabled && !is_vm0(vm)) {
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/* clear page entry for trusty */
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memset(pml4_addr + 6 * PAGE_SIZE_4K, 0, PAGE_SIZE_4K);
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/* Write PDPTE for trusy memory, PD will use 7th page */
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pd_base_paddr = GUEST_INIT_PAGE_TABLE_START +
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(6 * PAGE_SIZE_4K);
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table_offset =
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IA32E_PDPTE_INDEX_CALC(TRUSTY_EPT_REBASE_GPA);
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addr = (pml4_addr + PAGE_SIZE_4K + table_offset);
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table_present = (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT);
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entry = (pd_base_paddr | table_present);
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MEM_WRITE64(addr, entry);
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/* Write PDE for trusty with 2M page size */
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entry_num = TRUSTY_MEMORY_SIZE / (1 << MMU_PDE_PAGE_SHIFT);
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addr = pml4_addr + 6 * PAGE_SIZE_4K;
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table_present = (IA32E_PDPTE_PS_BIT
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| IA32E_COMM_P_BIT
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| IA32E_COMM_RW_BIT);
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for (i = 0; i < entry_num; i++) {
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entry = (TRUSTY_EPT_REBASE_GPA +
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(i * (1 << MMU_PDE_PAGE_SHIFT)))
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| table_present;
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MEM_WRITE64(addr, entry);
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addr += IA32E_COMM_ENTRY_SIZE;
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}
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}
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return GUEST_INIT_PAGE_TABLE_START;
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}
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@ -98,9 +98,10 @@ int create_vcpu(int cpu_id, struct vm *vm, struct vcpu **rtn_vcpu_handle)
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/* Is this VCPU a VM BSP, create page hierarchy for this VM */
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if (is_vcpu_bsp(vcpu)) {
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/* Set up temporary guest page tables */
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vm->arch_vm.guest_pml4 = create_guest_paging(vm);
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vm->arch_vm.guest_init_pml4 = create_guest_initial_paging(vm);
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pr_info("VM *d VCPU %d CR3: 0x%016llx ",
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vm->attr.id, vcpu->vcpu_id, vm->arch_vm.guest_pml4);
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vm->attr.id, vcpu->vcpu_id,
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vm->arch_vm.guest_init_pml4);
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}
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/* Allocate VMCS region for this VCPU */
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@ -38,9 +38,6 @@
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_Static_assert(NR_WORLD == 2, "Only 2 Worlds supported!");
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/* Trusty EPT rebase gpa: 511G */
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#define TRUSTY_EPT_REBASE_GPA (511ULL*1024ULL*1024ULL*1024ULL)
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#define TRUSTY_VERSION 1
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struct trusty_startup_param {
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@ -270,7 +270,7 @@ static void init_guest_state(struct vcpu *vcpu)
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} else if (get_vcpu_mode(vcpu) == PAGE_PROTECTED_MODE) {
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cur_context->cr0 = ((uint64_t)CR0_PG | CR0_PE | CR0_NE);
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cur_context->cr4 = ((uint64_t)CR4_PSE | CR4_PAE | CR4_MCE | CR4_VMXE);
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cur_context->cr3 = (uint64_t)vm->arch_vm.guest_pml4 | CR3_PWT;
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cur_context->cr3 = vm->arch_vm.guest_init_pml4 | CR3_PWT;
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}
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value = cur_context->cr0;
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@ -124,7 +124,7 @@ int load_guest(struct vm *vm, struct vcpu *vcpu)
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pr_info("VCPU%d Entry: 0x%llx, RSI: 0x%016llx, cr3: 0x%016llx",
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vcpu->vcpu_id, vcpu->entry_addr,
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cur_context->guest_cpu_regs.regs.rsi,
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vm->arch_vm.guest_pml4);
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vm->arch_vm.guest_init_pml4);
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return ret;
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}
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@ -43,6 +43,9 @@
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#define CPU_PAGE_SIZE 0x1000
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#define CPU_PAGE_MASK 0xFFFFFFFFFFFFF000
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#define MMU_PTE_PAGE_SHIFT CPU_PAGE_SHIFT
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#define MMU_PDE_PAGE_SHIFT 21
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/* Define CPU stack alignment */
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#define CPU_STACK_ALIGN 16
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@ -113,7 +113,7 @@ struct vm_state_info {
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};
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struct vm_arch {
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void *guest_pml4; /* Guest pml4 */
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uint64_t guest_init_pml4;/* Guest init pml4 */
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/* EPT hierarchy for Normal World */
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uint64_t nworld_eptp;
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/* EPT hierarchy for Secure World
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@ -381,7 +381,7 @@ extern uint8_t CPU_Boot_Page_Tables_Start_VM[];
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/* External Interfaces */
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int is_ept_supported(void);
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void *create_guest_paging(struct vm *vm);
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uint64_t create_guest_initial_paging(struct vm *vm);
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void destroy_ept(struct vm *vm);
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uint64_t gpa2hpa(struct vm *vm, uint64_t gpa);
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uint64_t gpa2hpa_check(struct vm *vm, uint64_t gpa,
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@ -36,6 +36,10 @@
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#define MMC_PROD_NAME_WITH_PSN_LEN 15
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#define BUP_MKHI_BOOTLOADER_SEED_LEN 64
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/* Trusty EPT rebase gpa: 511G */
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#define TRUSTY_EPT_REBASE_GPA (511ULL*1024ULL*1024ULL*1024ULL)
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#define TRUSTY_MEMORY_SIZE 0x01000000
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/* Structure of seed info */
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struct seed_info {
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uint8_t cse_svn;
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