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DM USB: xHCI: refine the PLC bit emulation logic during S3

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According to xHCI 5.4.8, the Port Link State Change (PLC) bit
should not be set to 1 during suspend process. This patch is used
to fix it.

Tracked-On: #1893
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Liang Yang <liang3.yang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This commit is contained in:
Xiaoguang Wu 2018-11-11 15:47:06 +08:00 committed by wenlingz
parent 29e81501c5
commit 9e471d7258
1 changed files with 9 additions and 2 deletions
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11
devicemodel/hw/pci/xhci.c
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@ -1262,8 +1262,15 @@ pci_xhci_portregs_write(struct pci_xhci_vdev *xdev,
case 3: /* U3 */
if (oldpls != newpls) {
p->portsc &= ~XHCI_PS_PLS_MASK;
p->portsc |= XHCI_PS_PLS_SET(newpls) |
XHCI_PS_PLC;
p->portsc |= XHCI_PS_PLS_SET(newpls);
/*
* TODO:
* Should check if this is exactly
* consistent with xHCI spec.
*/
if (newpls == 0)
p->portsc |= XHCI_PS_PLC;
if (oldpls != 0 && newpls == 0) {
pci_xhci_set_evtrb(&evtrb, port,