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hv: msr: use UL since ia32_misc_enable is 64bit

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Merge two parts of different definitions for MSR_IA32_MISC_ENABLE fields.
- use the prefix "MSR_IA32_" to align with others
- Change MSR_IA32_MISC_ENABLE_XD to MSR_IA32_MISC_ENABLE_XD_DISABLE to
  align the meaning of the filed since it is "XD bit disable"
Use UL instead of U as the filed bit mask because MSR_IA32_MISC_ENABLE is 64-bit.

Tracked-On: #2834
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Binbin Wu
2019-04-30 10:11:09 +08:00
committed by Eddie Dong
parent 7494ed2775
commit a0a6eb43c4
2 changed files with 13 additions and 16 deletions
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4
hypervisor/arch/x86/cpu_caps.c
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@@ -77,9 +77,9 @@ bool has_monitor_cap(void)
static inline bool is_fast_string_erms_supported_and_enabled(void)
{
bool ret = false;
uint32_t misc_enable = (uint32_t)msr_read(MSR_IA32_MISC_ENABLE);
uint64_t misc_enable = msr_read(MSR_IA32_MISC_ENABLE);
if ((misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) == 0U) {
if ((misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) == 0UL) {
pr_fatal("%s, fast string is not enabled\n", __func__);
} else {
if (!pcpu_has_cap(X86_FEATURE_ERMS)) {