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hv: msr: use UL since ia32_misc_enable is 64bit

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Merge two parts of different definitions for MSR_IA32_MISC_ENABLE fields.
- use the prefix "MSR_IA32_" to align with others
- Change MSR_IA32_MISC_ENABLE_XD to MSR_IA32_MISC_ENABLE_XD_DISABLE to
  align the meaning of the filed since it is "XD bit disable"
Use UL instead of U as the filed bit mask because MSR_IA32_MISC_ENABLE is 64-bit.

Tracked-On: #2834
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Binbin Wu 2019-04-30 10:11:09 +08:00 committed by Eddie Dong
parent 7494ed2775
commit a0a6eb43c4
2 changed files with 13 additions and 16 deletions
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4
hypervisor/arch/x86/cpu_caps.c
View File

@ -77,9 +77,9 @@ bool has_monitor_cap(void)
static inline bool is_fast_string_erms_supported_and_enabled(void) static inline bool is_fast_string_erms_supported_and_enabled(void)
{ {
bool ret = false; bool ret = false;
uint32_t misc_enable = (uint32_t)msr_read(MSR_IA32_MISC_ENABLE); uint64_t misc_enable = msr_read(MSR_IA32_MISC_ENABLE);
if ((misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) == 0U) { if ((misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) == 0UL) {
pr_fatal("%s, fast string is not enabled\n", __func__); pr_fatal("%s, fast string is not enabled\n", __func__);
} else { } else {
if (!pcpu_has_cap(X86_FEATURE_ERMS)) { if (!pcpu_has_cap(X86_FEATURE_ERMS)) {

25
hypervisor/include/arch/x86/msr.h
View File

@ -551,7 +551,17 @@
#define PAT_MEM_TYPE_UCM 0x07UL /* uncached minus */ #define PAT_MEM_TYPE_UCM 0x07UL /* uncached minus */
/* MISC_ENABLE bits: architectural */ /* MISC_ENABLE bits: architectural */
#define MSR_IA32_MISC_ENABLE_FAST_STRING (1U << 0U) #define MSR_IA32_MISC_ENABLE_FAST_STRING (1UL << 0U)
#define MSR_IA32_MISC_ENABLE_TCC (1UL << 3U)
#define MSR_IA32_MISC_ENABLE_PMA (1UL << 7U)
#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1UL << 11U)
#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1UL << 12U)
#define MSR_IA32_MISC_ENABLE_TM2_ENABLE (1UL << 13U)
#define MSR_IA32_MISC_ENABLE_EITS (1UL << 16U)
#define MSR_IA32_MISC_ENABLE_MONITOR_ENA (1UL << 18U)
#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1UL << 22U)
#define MSR_IA32_MISC_ENABLE_xTPR (1UL << 23U)
#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1UL << 34U)
#ifndef ASSEMBLER #ifndef ASSEMBLER
static inline bool pat_mem_type_invalid(uint64_t x) static inline bool pat_mem_type_invalid(uint64_t x)
@ -624,17 +634,4 @@ void update_msr_bitmap_x2apic_passthru(const struct acrn_vcpu *vcpu);
/* Flush L1 D-cache */ /* Flush L1 D-cache */
#define IA32_L1D_FLUSH (1UL << 0U) #define IA32_L1D_FLUSH (1UL << 0U)
/* MSR_IA32_MISC_ENABLE */
#define MISC_ENABLE_FAST_STRING (1U << 0U)
#define MISC_ENABLE_TCC (1U << 3U)
#define MISC_ENABLE_PMA (1U << 7U)
#define MISC_ENABLE_BTS_UNAVAIL (1U << 11U)
#define MISC_ENABLE_PEBS_UNAVAIL (1U << 12U)
#define MISC_ENABLE_TM2_ENABLE (1U << 13U)
#define MISC_ENABLE_EITS (1U << 16U)
#define MISC_ENABLE_MONITOR_ENA (1U << 18U)
#define MISC_ENABLE_LIMIT_CPUID (1U << 22U)
#define MISC_ENABLE_xTPR (1U << 23U)
#define MISC_ENABLE_XD (1U << 34U)
#endif /* MSR_H */ #endif /* MSR_H */