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hv: apicv: change the name of vapic to apicv

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Remove the vapic name and unify to apicv.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Yu Wang 2018-08-22 14:25:39 +00:00 committed by lijinxia
parent a0c625b85a
commit a6c2065b2e
5 changed files with 28 additions and 28 deletions
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24
hypervisor/arch/x86/cpu.c
View File

@ -40,7 +40,7 @@ bool x2apic_enabled = false;
#define VAPIC_FEATURE_VX2APIC_MODE (1U << 5)
struct cpu_capability {
uint8_t vapic_features;
uint8_t apicv_features;
uint8_t ept_features;
};
static struct cpu_capability cpu_caps;
@ -785,7 +785,7 @@ static void ept_cap_detect(void)
cpu_caps.ept_features = 1U;
}
static void vapic_cap_detect(void)
static void apicv_cap_detect(void)
{
uint8_t features;
uint64_t msr_val;
@ -794,14 +794,14 @@ static void vapic_cap_detect(void)
msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS);
if (!is_ctrl_setting_allowed(msr_val, VMX_PROCBASED_CTLS_TPR_SHADOW)) {
cpu_caps.vapic_features = 0U;
cpu_caps.apicv_features = 0U;
return;
}
features |= VAPIC_FEATURE_TPR_SHADOW;
msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS2);
if (!is_ctrl_setting_allowed(msr_val, VMX_PROCBASED_CTLS2_VAPIC)) {
cpu_caps.vapic_features = features;
cpu_caps.apicv_features = features;
return;
}
features |= VAPIC_FEATURE_VIRT_ACCESS;
@ -824,12 +824,12 @@ static void vapic_cap_detect(void)
}
}
cpu_caps.vapic_features = features;
cpu_caps.apicv_features = features;
}
static void cpu_cap_detect(void)
{
vapic_cap_detect();
apicv_cap_detect();
ept_cap_detect();
}
@ -838,19 +838,19 @@ bool is_ept_supported(void)
return (cpu_caps.ept_features != 0U);
}
bool is_vapic_supported(void)
bool is_apicv_supported(void)
{
return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_ACCESS) != 0U);
return ((cpu_caps.apicv_features & VAPIC_FEATURE_VIRT_ACCESS) != 0U);
}
bool is_vapic_intr_delivery_supported(void)
bool is_apicv_intr_delivery_supported(void)
{
return ((cpu_caps.vapic_features & VAPIC_FEATURE_INTR_DELIVERY) != 0U);
return ((cpu_caps.apicv_features & VAPIC_FEATURE_INTR_DELIVERY) != 0U);
}
bool is_vapic_virt_reg_supported(void)
bool is_apicv_virt_reg_supported(void)
{
return ((cpu_caps.vapic_features & VAPIC_FEATURE_VIRT_REG) != 0U);
return ((cpu_caps.apicv_features & VAPIC_FEATURE_VIRT_REG) != 0U);
}
static void cpu_xsave_init(void)

12
hypervisor/arch/x86/guest/vlapic.c
View File

@ -1198,7 +1198,7 @@ vlapic_icrlo_write_handler(struct acrn_vlapic *vlapic)
target_vcpu->vm->vm_id);
schedule_vcpu(target_vcpu);
} else if (mode == APIC_DELMODE_SMI) {
pr_info("vmx vapic: SMI IPI do not support\n");
pr_info("vlapic: SMI IPI do not support\n");
} else {
pr_err("Unhandled icrlo write with mode %u\n", mode);
}
@ -1924,7 +1924,7 @@ vlapic_rdmsr(struct vcpu *vcpu, uint32_t msr, uint64_t *rval)
default:
dev_dbg(ACRN_DBG_LAPIC,
"Invalid vmx vapic msr 0x%x access\n", msr);
"Invalid vlapic msr 0x%x access\n", msr);
break;
}
@ -1950,7 +1950,7 @@ vlapic_wrmsr(struct vcpu *vcpu, uint32_t msr, uint64_t wval)
default:
dev_dbg(ACRN_DBG_LAPIC,
"Invalid vmx vapic msr 0x%x access\n", msr);
"Invalid vlapic msr 0x%x access\n", msr);
break;
}
@ -2041,8 +2041,8 @@ int vlapic_create(struct vcpu *vcpu)
ASSERT(vlapic != NULL, "vlapic allocate failed");
vlapic->vm = vcpu->vm;
vlapic->vcpu = vcpu;
if (is_vapic_supported()) {
if (is_vapic_intr_delivery_supported()) {
if (is_apicv_supported()) {
if (is_apicv_intr_delivery_supported()) {
vlapic->ops.apicv_set_intr_ready_fn =
apicv_set_intr_ready;
@ -2095,7 +2095,7 @@ void vlapic_free(struct vcpu *vcpu)
del_timer(&vlapic->vtimer.timer);
if (!is_vapic_supported()) {
if (!is_apicv_supported()) {
unregister_mmio_emulation_handler(vcpu->vm,
(uint64_t)DEFAULT_APIC_BASE,
(uint64_t)DEFAULT_APIC_BASE + CPU_PAGE_SIZE);

2
hypervisor/arch/x86/virq.c
View File

@ -115,7 +115,7 @@ static int vcpu_do_pending_event(struct vcpu *vcpu)
uint32_t vector = 0U;
int ret = 0;
if (is_vapic_intr_delivery_supported()) {
if (is_apicv_intr_delivery_supported()) {
vlapic_apicv_inject_pir(vlapic);
return 0;
}

12
hypervisor/arch/x86/vmx.c
View File

@ -966,7 +966,7 @@ static void init_exec_ctrl(struct vcpu *vcpu)
*/
value32 &= ~VMX_PROCBASED_CTLS_INVLPG;
if (is_vapic_supported()) {
if (is_apicv_supported()) {
value32 |= VMX_PROCBASED_CTLS_TPR_SHADOW;
} else {
/* Add CR8 VMExit for vlapic */
@ -993,14 +993,14 @@ static void init_exec_ctrl(struct vcpu *vcpu)
value32 &= ~VMX_PROCBASED_CTLS2_VPID;
}
if (is_vapic_supported()) {
if (is_apicv_supported()) {
value32 |= VMX_PROCBASED_CTLS2_VAPIC;
if (is_vapic_virt_reg_supported()) {
if (is_apicv_virt_reg_supported()) {
value32 |= VMX_PROCBASED_CTLS2_VAPIC_REGS;
}
if (is_vapic_intr_delivery_supported()) {
if (is_apicv_intr_delivery_supported()) {
value32 |= VMX_PROCBASED_CTLS2_VIRQ;
}
else {
@ -1024,7 +1024,7 @@ static void init_exec_ctrl(struct vcpu *vcpu)
exec_vmwrite32(VMX_PROC_VM_EXEC_CONTROLS2, value32);
pr_dbg("VMX_PROC_VM_EXEC_CONTROLS2: 0x%x ", value32);
if (is_vapic_supported()) {
if (is_apicv_supported()) {
/*APIC-v, config APIC-access address*/
value64 = vlapic_apicv_get_apic_access_addr(vcpu->vm);
exec_vmwrite64(VMX_APIC_ACCESS_ADDR_FULL,
@ -1036,7 +1036,7 @@ static void init_exec_ctrl(struct vcpu *vcpu)
exec_vmwrite64(VMX_VIRTUAL_APIC_PAGE_ADDR_FULL,
value64);
if (is_vapic_intr_delivery_supported()) {
if (is_apicv_intr_delivery_supported()) {
/* Disable all EOI VMEXIT by default and
* clear RVI and SVI.
*/

6
hypervisor/include/arch/x86/cpu.h
View File

@ -323,9 +323,9 @@ extern struct cpuinfo_x86 boot_cpu_data;
void cpu_do_idle(__unused uint16_t pcpu_id);
void cpu_dead(uint16_t pcpu_id);
void trampoline_start16(void);
bool is_vapic_supported(void);
bool is_vapic_intr_delivery_supported(void);
bool is_vapic_virt_reg_supported(void);
bool is_apicv_supported(void);
bool is_apicv_intr_delivery_supported(void);
bool is_apicv_virt_reg_supported(void);
bool is_ept_supported(void);
bool cpu_has_cap(uint32_t bit);
void load_cpu_state_data(void);