mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-07-31 15:30:56 +00:00
hv: vlapic: remove vcpu/vm structure pointer from vlapic
We could use container_of to get vcpu/vm structure pointer from vlapic. So vcpu/vm structure pointer is no need in vlapic structure. Tracked-On: #4550 Signed-off-by: Li Fei1 <fei1.li@intel.com>
This commit is contained in:
parent
7f342bf62f
commit
a7768fdb6a
@ -64,6 +64,11 @@ static inline uint32_t prio(uint32_t x)
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#define DBG_LEVEL_VLAPIC 6U
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static inline struct acrn_vcpu *vlapic2vcpu(const struct acrn_vlapic *vlapic)
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{
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return container_of(container_of(vlapic, struct acrn_vcpu_arch, vlapic), struct acrn_vcpu, arch);
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}
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#if VLAPIC_VERBOS
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static inline void vlapic_dump_irr(const struct acrn_vlapic *vlapic, const char *msg)
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{
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@ -165,7 +170,7 @@ vlapic_get_apicid(const struct acrn_vlapic *vlapic)
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static inline uint32_t
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vlapic_build_id(const struct acrn_vlapic *vlapic)
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{
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const struct acrn_vcpu *vcpu = vlapic->vcpu;
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const struct acrn_vcpu *vcpu = vlapic2vcpu(vlapic);
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uint32_t vlapic_id, lapic_regs_id;
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if (is_sos_vm(vcpu->vm)) {
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@ -299,7 +304,7 @@ static void vlapic_init_timer(struct acrn_vlapic *vlapic)
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(void)memset(vtimer, 0U, sizeof(struct vlapic_timer));
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initialize_timer(&vtimer->timer,
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vlapic_timer_expired, vlapic->vcpu,
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vlapic_timer_expired, vlapic2vcpu(vlapic),
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0UL, 0, 0UL);
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}
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@ -427,23 +432,24 @@ static void vlapic_write_icrtmr(struct acrn_vlapic *vlapic)
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uint64_t vlapic_get_tsc_deadline_msr(const struct acrn_vlapic *vlapic)
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{
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uint64_t ret;
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struct acrn_vcpu *vcpu = vlapic2vcpu(vlapic);
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if (is_lapic_pt_enabled(vlapic->vcpu)) {
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if (is_lapic_pt_enabled(vcpu)) {
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/* If physical TSC_DEADLINE is zero which means it's not armed (automatically disarmed
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* after timer triggered), return 0 and reset the virtual TSC_DEADLINE;
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* If physical TSC_DEADLINE is not zero, return the virtual TSC_DEADLINE value.
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*/
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if (msr_read(MSR_IA32_TSC_DEADLINE) == 0UL) {
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vcpu_set_guest_msr(vlapic->vcpu, MSR_IA32_TSC_DEADLINE, 0UL);
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vcpu_set_guest_msr(vcpu, MSR_IA32_TSC_DEADLINE, 0UL);
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ret = 0UL;
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} else {
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ret = vcpu_get_guest_msr(vlapic->vcpu, MSR_IA32_TSC_DEADLINE);
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ret = vcpu_get_guest_msr(vcpu, MSR_IA32_TSC_DEADLINE);
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}
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} else if (!vlapic_lvtt_tsc_deadline(vlapic)) {
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ret = 0UL;
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} else {
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ret = (vlapic->vtimer.timer.fire_tsc == 0UL) ? 0UL :
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vcpu_get_guest_msr(vlapic->vcpu, MSR_IA32_TSC_DEADLINE);
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vcpu_get_guest_msr(vcpu, MSR_IA32_TSC_DEADLINE);
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}
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return ret;
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@ -453,9 +459,10 @@ void vlapic_set_tsc_deadline_msr(struct acrn_vlapic *vlapic, uint64_t val_arg)
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{
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struct hv_timer *timer;
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uint64_t val = val_arg;
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struct acrn_vcpu *vcpu = vlapic2vcpu(vlapic);
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if (is_lapic_pt_enabled(vlapic->vcpu)) {
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vcpu_set_guest_msr(vlapic->vcpu, MSR_IA32_TSC_DEADLINE, val);
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if (is_lapic_pt_enabled(vcpu)) {
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vcpu_set_guest_msr(vcpu, MSR_IA32_TSC_DEADLINE, val);
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/* If val is not zero, which mean guest intends to arm the tsc_deadline timer,
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* if the calculated value to write to the physical TSC_DEADLINE msr is zero,
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* we plus 1 to not disarm the physcial timer falsely;
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@ -472,7 +479,7 @@ void vlapic_set_tsc_deadline_msr(struct acrn_vlapic *vlapic, uint64_t val_arg)
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msr_write(MSR_IA32_TSC_DEADLINE, 0);
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}
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} else if (vlapic_lvtt_tsc_deadline(vlapic)) {
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vcpu_set_guest_msr(vlapic->vcpu, MSR_IA32_TSC_DEADLINE, val);
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vcpu_set_guest_msr(vcpu, MSR_IA32_TSC_DEADLINE, val);
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timer = &vlapic->vtimer.timer;
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del_timer(timer);
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@ -510,11 +517,11 @@ vlapic_set_tmr(struct acrn_vlapic *vlapic, uint32_t vector, bool level)
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struct lapic_reg *tmrptr = &(vlapic->apic_page.tmr[0]);
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if (level) {
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if (!bitmap32_test_and_set_lock((uint16_t)(vector & 0x1fU), &tmrptr[(vector & 0xffU) >> 5U].v)) {
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vcpu_set_eoi_exit_bitmap(vlapic->vcpu, vector);
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vcpu_set_eoi_exit_bitmap(vlapic2vcpu(vlapic), vector);
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}
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} else {
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if (bitmap32_test_and_clear_lock((uint16_t)(vector & 0x1fU), &tmrptr[(vector & 0xffU) >> 5U].v)) {
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vcpu_clear_eoi_exit_bitmap(vlapic->vcpu, vector);
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vcpu_clear_eoi_exit_bitmap(vlapic2vcpu(vlapic), vector);
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}
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}
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}
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@ -533,7 +540,7 @@ vlapic_reset_tmr(struct acrn_vlapic *vlapic)
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lapic->tmr[i].v = 0U;
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}
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vcpu_reset_eoi_exit_bitmaps(vlapic->vcpu);
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vcpu_reset_eoi_exit_bitmaps(vlapic2vcpu(vlapic));
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}
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static void apicv_basic_accept_intr(struct acrn_vlapic *vlapic, uint32_t vector, bool level)
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@ -550,7 +557,7 @@ static void apicv_basic_accept_intr(struct acrn_vlapic *vlapic, uint32_t vector,
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if (!bitmap32_test_and_set_lock((uint16_t)(vector & 0x1fU), &irrptr[idx].v)) {
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/* update TMR if interrupt trigger mode has changed */
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vlapic_set_tmr(vlapic, vector, level);
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vcpu_make_request(vlapic->vcpu, ACRN_REQUEST_EVENT);
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vcpu_make_request(vlapic2vcpu(vlapic), ACRN_REQUEST_EVENT);
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}
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}
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@ -560,6 +567,7 @@ static void apicv_advanced_accept_intr(struct acrn_vlapic *vlapic, uint32_t vect
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vlapic_set_tmr(vlapic, vector, level);
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if (apicv_set_intr_ready(vlapic, vector)) {
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struct acrn_vcpu *vcpu = vlapic2vcpu(vlapic);
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/*
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* Send interrupt to vCPU via posted interrupt way:
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* 1. If target vCPU is in root mode(isn't running),
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@ -570,10 +578,10 @@ static void apicv_advanced_accept_intr(struct acrn_vlapic *vlapic, uint32_t vect
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* send PI notification to vCPU and hardware will
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* sync PIR to vIRR automatically.
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*/
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bitmap_set_lock(ACRN_REQUEST_EVENT, &vlapic->vcpu->arch.pending_req);
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bitmap_set_lock(ACRN_REQUEST_EVENT, &vcpu->arch.pending_req);
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if (get_pcpu_id() != pcpuid_from_vcpu(vlapic->vcpu)) {
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apicv_post_intr(pcpuid_from_vcpu(vlapic->vcpu));
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if (get_pcpu_id() != pcpuid_from_vcpu(vcpu)) {
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apicv_post_intr(pcpuid_from_vcpu(vcpu));
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}
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}
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}
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@ -590,7 +598,7 @@ static void vlapic_accept_intr(struct acrn_vlapic *vlapic, uint32_t vector, bool
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if ((lapic->svr.v & APIC_SVR_ENABLE) == 0U) {
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dev_dbg(DBG_LEVEL_VLAPIC, "vlapic is software disabled, ignoring interrupt %u", vector);
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} else {
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signal_event(&vlapic->vcpu->events[VCPU_EVENT_VIRTUAL_INTERRUPT]);
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signal_event(&vlapic2vcpu(vlapic)->events[VCPU_EVENT_VIRTUAL_INTERRUPT]);
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vlapic->ops->accept_intr(vlapic, vector, level);
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}
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}
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@ -738,12 +746,13 @@ vlapic_write_lvt(struct acrn_vlapic *vlapic, uint32_t offset)
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if ((offset == APIC_OFFSET_LINT0_LVT) &&
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((val & APIC_LVT_DM) == APIC_LVT_DM_EXTINT)) {
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uint32_t last = vlapic_get_lvt(vlapic, offset);
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struct acrn_vm *vm = vlapic2vcpu(vlapic)->vm;
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/* mask -> unmask: may from every vlapic in the vm */
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if (((last & APIC_LVT_M) != 0U) && ((val & APIC_LVT_M) == 0U)) {
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if ((vlapic->vm->wire_mode == VPIC_WIRE_INTR) ||
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(vlapic->vm->wire_mode == VPIC_WIRE_NULL)) {
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vlapic->vm->wire_mode = VPIC_WIRE_LAPIC;
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if ((vm->wire_mode == VPIC_WIRE_INTR) ||
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(vm->wire_mode == VPIC_WIRE_NULL)) {
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vm->wire_mode = VPIC_WIRE_LAPIC;
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dev_dbg(DBG_LEVEL_VLAPIC,
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"vpic wire mode -> LAPIC");
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} else {
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@ -752,8 +761,8 @@ vlapic_write_lvt(struct acrn_vlapic *vlapic, uint32_t offset)
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}
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/* unmask -> mask: only from the vlapic LINT0-ExtINT enabled */
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} else if (((last & APIC_LVT_M) == 0U) && ((val & APIC_LVT_M) != 0U)) {
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if (vlapic->vm->wire_mode == VPIC_WIRE_LAPIC) {
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vlapic->vm->wire_mode = VPIC_WIRE_NULL;
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if (vm->wire_mode == VPIC_WIRE_LAPIC) {
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vm->wire_mode = VPIC_WIRE_NULL;
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dev_dbg(DBG_LEVEL_VLAPIC,
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"vpic wire mode -> NULL");
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}
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@ -806,13 +815,10 @@ vlapic_mask_lvts(struct acrn_vlapic *vlapic)
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static void
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vlapic_fire_lvt(struct acrn_vlapic *vlapic, uint32_t lvt)
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{
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uint32_t vec, mode;
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struct acrn_vcpu *vcpu = vlapic->vcpu;
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if ((lvt & APIC_LVT_M) == 0U) {
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vec = lvt & APIC_LVT_VECTOR;
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mode = lvt & APIC_LVT_DM;
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struct acrn_vcpu *vcpu = vlapic2vcpu(vlapic);
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uint32_t vec = lvt & APIC_LVT_VECTOR;
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uint32_t mode = lvt & APIC_LVT_DM;
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switch (mode) {
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case APIC_LVT_DM_FIXED:
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@ -884,10 +890,10 @@ vlapic_process_eoi(struct acrn_vlapic *vlapic)
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* Register of the LAPIC.
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* TODO: Check if the bit 12 "Suppress EOI Broadcasts" is set.
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*/
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vioapic_broadcast_eoi(vlapic->vm, vector);
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vioapic_broadcast_eoi(vlapic2vcpu(vlapic)->vm, vector);
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}
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vcpu_make_request(vlapic->vcpu, ACRN_REQUEST_EVENT);
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vcpu_make_request(vlapic2vcpu(vlapic), ACRN_REQUEST_EVENT);
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}
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dev_dbg(DBG_LEVEL_VLAPIC, "Gratuitous EOI");
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@ -921,9 +927,9 @@ vlapic_trigger_lvt(struct acrn_vlapic *vlapic, uint32_t lvt_index)
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{
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uint32_t lvt;
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int32_t ret = 0;
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struct acrn_vcpu *vcpu = vlapic->vcpu;
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if (vlapic_enabled(vlapic) == false) {
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struct acrn_vcpu *vcpu = vlapic2vcpu(vlapic);
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/*
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* When the local APIC is global/hardware disabled,
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* LINT[1:0] pins are configured as INTR and NMI pins,
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@ -1094,7 +1100,7 @@ vlapic_calc_dest(struct acrn_vm *vm, uint64_t *dmask, bool is_broadcast,
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}
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if (lowprio && (lowprio_dest != NULL)) {
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bitmap_set_nolock(lowprio_dest->vcpu->vcpu_id, dmask);
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bitmap_set_nolock(vlapic2vcpu(lowprio_dest)->vcpu_id, dmask);
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}
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}
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}
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@ -1220,6 +1226,7 @@ static void vlapic_write_icrlo(struct acrn_vlapic *vlapic)
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|| (mode == APIC_DELMODE_STARTUP))) {
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dev_dbg(DBG_LEVEL_VLAPIC, "Invalid ICR value");
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} else {
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struct acrn_vcpu *vcpu = vlapic2vcpu(vlapic);
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dev_dbg(DBG_LEVEL_VLAPIC,
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"icrlo 0x%08x icrhi 0x%08x triggered ipi %u",
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@ -1227,17 +1234,17 @@ static void vlapic_write_icrlo(struct acrn_vlapic *vlapic)
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switch (shorthand) {
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case APIC_DEST_DESTFLD:
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vlapic_calc_dest(vlapic->vm, &dmask, is_broadcast, dest, phys, false);
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vlapic_calc_dest(vcpu->vm, &dmask, is_broadcast, dest, phys, false);
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break;
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case APIC_DEST_SELF:
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bitmap_set_nolock(vlapic->vcpu->vcpu_id, &dmask);
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bitmap_set_nolock(vcpu->vcpu_id, &dmask);
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break;
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case APIC_DEST_ALLISELF:
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dmask = vm_active_cpus(vlapic->vm);
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dmask = vm_active_cpus(vcpu->vm);
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break;
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case APIC_DEST_ALLESELF:
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dmask = vm_active_cpus(vlapic->vm);
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bitmap_clear_nolock(vlapic->vcpu->vcpu_id, &dmask);
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dmask = vm_active_cpus(vcpu->vm);
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bitmap_clear_nolock(vlapic2vcpu(vlapic)->vcpu_id, &dmask);
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break;
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default:
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/*
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@ -1247,9 +1254,9 @@ static void vlapic_write_icrlo(struct acrn_vlapic *vlapic)
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break;
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}
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for (vcpu_id = 0U; vcpu_id < vlapic->vm->hw.created_vcpus; vcpu_id++) {
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for (vcpu_id = 0U; vcpu_id < vcpu->vm->hw.created_vcpus; vcpu_id++) {
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if ((dmask & (1UL << vcpu_id)) != 0UL) {
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target_vcpu = vcpu_from_vid(vlapic->vm, vcpu_id);
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target_vcpu = vcpu_from_vid(vcpu->vm, vcpu_id);
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if (mode == APIC_DELMODE_FIXED) {
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vlapic_set_intr(target_vcpu, vec, LAPIC_TRIG_EDGE);
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@ -1385,6 +1392,7 @@ vlapic_write_svr(struct acrn_vlapic *vlapic)
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changed = old ^ new;
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if ((changed & APIC_SVR_ENABLE) != 0U) {
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if ((new & APIC_SVR_ENABLE) == 0U) {
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struct acrn_vm *vm = vlapic2vcpu(vlapic)->vm;
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/*
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* The apic is now disabled so stop the apic timer
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* and mask all the LVT entries.
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@ -1394,8 +1402,8 @@ vlapic_write_svr(struct acrn_vlapic *vlapic)
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vlapic_mask_lvts(vlapic);
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/* the only one enabled LINT0-ExtINT vlapic disabled */
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if (vlapic->vm->wire_mode == VPIC_WIRE_NULL) {
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vlapic->vm->wire_mode = VPIC_WIRE_INTR;
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if (vm->wire_mode == VPIC_WIRE_NULL) {
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vm->wire_mode = VPIC_WIRE_INTR;
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dev_dbg(DBG_LEVEL_VLAPIC,
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"vpic wire mode -> INTR");
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}
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@ -1637,7 +1645,7 @@ vlapic_reset(struct acrn_vlapic *vlapic, const struct acrn_apicv_ops *ops, enum
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vlapic->msr_apicbase = DEFAULT_APIC_BASE;
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if (vlapic->vcpu->vcpu_id == BSP_CPU_ID) {
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if (vlapic2vcpu(vlapic)->vcpu_id == BSP_CPU_ID) {
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vlapic->msr_apicbase |= APICBASE_BSP;
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}
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if (mode == INIT_RESET) {
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@ -1681,8 +1689,8 @@ vlapic_reset(struct acrn_vlapic *vlapic, const struct acrn_apicv_ops *ops, enum
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}
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/**
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* @pre vlapic->vm != NULL
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* @pre vlapic->vcpu->vcpu_id < MAX_VCPUS_PER_VM
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* @pre vlapic-...->vm != NULL
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* @pre vlapic-...->vcpu->vcpu_id < MAX_VCPUS_PER_VM
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*/
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void
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vlapic_init(struct acrn_vlapic *vlapic)
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@ -1725,13 +1733,13 @@ uint64_t vlapic_get_apicbase(const struct acrn_vlapic *vlapic)
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static void ptapic_accept_intr(struct acrn_vlapic *vlapic, uint32_t vector, __unused bool level)
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{
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pr_err("Invalid op %s, VM%u, vCPU%u, vector %u", __func__,
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vlapic->vm->vm_id, vlapic->vcpu->vcpu_id, vector);
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vlapic2vcpu(vlapic)->vm->vm_id, vlapic2vcpu(vlapic)->vcpu_id, vector);
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}
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static bool ptapic_inject_intr(struct acrn_vlapic *vlapic,
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__unused bool guest_irq_enabled, __unused bool injected)
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{
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pr_err("Invalid op %s, VM%u, vCPU%u", __func__, vlapic->vm->vm_id, vlapic->vcpu->vcpu_id);
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pr_err("Invalid op %s, VM%u, vCPU%u", __func__, vlapic2vcpu(vlapic)->vm->vm_id, vlapic2vcpu(vlapic)->vcpu_id);
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return injected;
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}
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@ -1766,8 +1774,6 @@ int32_t vlapic_set_apicbase(struct acrn_vlapic *vlapic, uint64_t new)
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int32_t ret = 0;
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uint64_t changed;
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bool change_in_vlapic_mode = false;
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struct acrn_vcpu *vcpu = vlapic->vcpu;
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if (vlapic->msr_apicbase != new) {
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changed = vlapic->msr_apicbase ^ new;
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@ -1777,20 +1783,21 @@ int32_t vlapic_set_apicbase(struct acrn_vlapic *vlapic, uint64_t new)
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* TODO: Logic to check for change in Reserved Bits and Inject GP
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*/
|
||||
|
||||
|
||||
/*
|
||||
* Logic to check for change in Bits 11:10 for vLAPIC mode switch
|
||||
*/
|
||||
if (change_in_vlapic_mode) {
|
||||
if ((new & APICBASE_LAPIC_MODE) ==
|
||||
(APICBASE_XAPIC | APICBASE_X2APIC)) {
|
||||
struct acrn_vcpu *vcpu = vlapic2vcpu(vlapic);
|
||||
|
||||
if (is_lapic_pt_configured(vcpu->vm)) {
|
||||
/* vlapic need to be reset to make sure it is in correct state */
|
||||
vlapic_reset(vlapic, &ptapic_ops, SOFTWARE_RESET);
|
||||
}
|
||||
vlapic->msr_apicbase = new;
|
||||
vlapic_build_x2apic_id(vlapic);
|
||||
switch_apicv_mode_x2apic(vlapic->vcpu);
|
||||
switch_apicv_mode_x2apic(vcpu);
|
||||
update_vm_vlapic_state(vcpu->vm);
|
||||
} else {
|
||||
/*
|
||||
@ -2170,9 +2177,6 @@ int32_t vlapic_x2apic_write(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t val)
|
||||
|
||||
void vlapic_create(struct acrn_vcpu *vcpu)
|
||||
{
|
||||
vcpu->arch.vlapic.vm = vcpu->vm;
|
||||
vcpu->arch.vlapic.vcpu = vcpu;
|
||||
|
||||
if (is_vcpu_bsp(vcpu)) {
|
||||
uint64_t *pml4_page =
|
||||
(uint64_t *)vcpu->vm->arch_vm.nworld_eptp;
|
||||
@ -2497,7 +2501,7 @@ int32_t veoi_vmexit_handler(struct acrn_vcpu *vcpu)
|
||||
|
||||
if (bitmap32_test((uint16_t)(vector & 0x1fU), &tmrptr[idx].v)) {
|
||||
/* hook to vIOAPIC */
|
||||
vioapic_broadcast_eoi(vlapic->vm, vector);
|
||||
vioapic_broadcast_eoi(vcpu->vm, vector);
|
||||
}
|
||||
|
||||
TRACE_2L(TRACE_VMEXIT_APICV_VIRT_EOI, vector, 0UL);
|
||||
@ -2509,16 +2513,14 @@ static void vlapic_x2apic_self_ipi_handler(struct acrn_vlapic *vlapic)
|
||||
{
|
||||
struct lapic_regs *lapic;
|
||||
uint32_t vector;
|
||||
struct acrn_vcpu *target_vcpu;
|
||||
|
||||
lapic = &(vlapic->apic_page);
|
||||
vector = lapic->self_ipi.v & APIC_VECTOR_MASK;
|
||||
target_vcpu = vlapic->vcpu;
|
||||
if (vector < 16U) {
|
||||
vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR);
|
||||
dev_dbg(DBG_LEVEL_VLAPIC, "Ignoring invalid IPI %u", vector);
|
||||
} else {
|
||||
vlapic_set_intr(target_vcpu, vector, LAPIC_TRIG_EDGE);
|
||||
vlapic_set_intr(vlapic2vcpu(vlapic), vector, LAPIC_TRIG_EDGE);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -61,9 +61,6 @@ struct acrn_vlapic {
|
||||
*/
|
||||
struct lapic_regs apic_page;
|
||||
|
||||
struct acrn_vm *vm;
|
||||
struct acrn_vcpu *vcpu;
|
||||
|
||||
uint32_t esr_pending;
|
||||
int32_t esr_firing;
|
||||
|
||||
@ -88,6 +85,8 @@ struct acrn_vlapic {
|
||||
uint32_t lvt_last[VLAPIC_MAXLVT_INDEX + 1];
|
||||
} __aligned(PAGE_SIZE);
|
||||
|
||||
|
||||
struct acrn_vcpu;
|
||||
struct acrn_apicv_ops {
|
||||
void (*accept_intr)(struct acrn_vlapic *vlapic, uint32_t vector, bool level);
|
||||
bool (*inject_intr)(struct acrn_vlapic *vlapic, bool guest_irq_enabled, bool injected);
|
||||
|
Loading…
Reference in New Issue
Block a user