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HV: treewide: convert hexadecimals used in bitops to unsigned

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Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao
2018-06-19 18:33:58 +08:00
committed by lijinxia
parent cdd38d0bc3
commit aa505a28bb
29 changed files with 258 additions and 258 deletions
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24
hypervisor/arch/x86/assign.c
View File

@@ -202,7 +202,7 @@ static void ptdev_build_physical_msi(struct vm *vm, struct ptdev_msi_info *info,
bool phys;
/* get physical destination cpu mask */
dest = (info->vmsi_addr >> 12) & 0xff;
dest = (info->vmsi_addr >> 12) & 0xffU;
phys = ((info->vmsi_addr &
(MSI_ADDR_RH | MSI_ADDR_LOG)) !=
(MSI_ADDR_RH | MSI_ADDR_LOG));
@@ -216,12 +216,12 @@ static void ptdev_build_physical_msi(struct vm *vm, struct ptdev_msi_info *info,
/* update physical delivery mode & vector */
info->pmsi_data = info->vmsi_data;
info->pmsi_data &= ~0x7FF;
info->pmsi_data &= ~0x7FFU;
info->pmsi_data |= delmode | vector;
/* update physical dest mode & dest field */
info->pmsi_addr = info->vmsi_addr;
info->pmsi_addr &= ~0xFF00C;
info->pmsi_addr &= ~0xFF00CU;
info->pmsi_addr |= pdmask << 12 |
MSI_ADDR_RH | MSI_ADDR_LOG;
@@ -636,7 +636,7 @@ int ptdev_msix_remap(struct vm *vm, uint16_t virt_bdf,
/* build physical config MSI, update to info->pmsi_xxx */
ptdev_build_physical_msi(vm, info, dev_to_vector(entry->node));
entry->ptdev_intr_info.msi = *info;
entry->ptdev_intr_info.msi.virt_vector = info->vmsi_data & 0xFF;
entry->ptdev_intr_info.msi.virt_vector = info->vmsi_data & 0xFFU;
entry->ptdev_intr_info.msi.phys_vector = dev_to_vector(entry->node);
/* update irq handler according to info in guest */
@@ -644,9 +644,9 @@ int ptdev_msix_remap(struct vm *vm, uint16_t virt_bdf,
dev_dbg(ACRN_DBG_IRQ,
"PCI %x:%x.%x MSI VR[%d] 0x%x->0x%x assigned to vm%d",
(entry->virt_bdf >> 8) & 0xFF,
(entry->virt_bdf >> 3) & 0x1F,
(entry->virt_bdf) & 0x7,
(entry->virt_bdf >> 8) & 0xFFU,
(entry->virt_bdf >> 3) & 0x1FU,
(entry->virt_bdf) & 0x7U,
entry->ptdev_intr_info.msi.msix_entry_index,
entry->ptdev_intr_info.msi.virt_vector,
entry->ptdev_intr_info.msi.phys_vector,
@@ -920,7 +920,7 @@ static void get_entry_info(struct ptdev_remapping_info *entry, char *type,
if (is_entry_active(entry)) {
if (entry->type == PTDEV_INTR_MSI) {
strcpy_s(type, 16, "MSI");
*dest = (entry->ptdev_intr_info.msi.pmsi_addr & 0xFF000)
*dest = (entry->ptdev_intr_info.msi.pmsi_addr & 0xFF000U)
>> 12;
if ((entry->ptdev_intr_info.msi.pmsi_data &
APIC_TRIGMOD_LEVEL) != 0U)
@@ -1003,10 +1003,10 @@ void get_ptdev_info(char *str, int str_max)
is_entry_active(entry) ?
(lvl_tm ? "level" : "edge") : "none",
pin, vpin,
(bdf & 0xff00) >> 8,
(bdf & 0xf8) >> 3, bdf & 0x7,
(vbdf & 0xff00) >> 8,
(vbdf & 0xf8) >> 3, vbdf & 0x7);
(bdf & 0xff00U) >> 8,
(bdf & 0xf8U) >> 3, bdf & 0x7U,
(vbdf & 0xff00U) >> 8,
(vbdf & 0xf8U) >> 3, vbdf & 0x7U);
size -= len;
str += len;
}

10
hypervisor/arch/x86/guest/guest.c
View File

@@ -31,7 +31,7 @@ struct page_walk_info {
inline bool
is_vm0(struct vm *vm)
{
return (vm->attr.boot_idx & 0x7F) == 0;
return (vm->attr.boot_idx & 0x7FU) == 0;
}
inline struct vcpu *vcpu_from_vid(struct vm *vm, int vcpu_id)
@@ -206,14 +206,14 @@ static int _gva2gpa_pae(struct vcpu *vcpu, struct page_walk_info *pw_info,
uint64_t addr;
int ret;
addr = pw_info->top_entry & 0xFFFFFFF0UL;
addr = pw_info->top_entry & 0xFFFFFFF0U;
base = GPA2HVA(vcpu->vm, addr);
if (base == NULL) {
ret = -EFAULT;
goto out;
}
index = (gva >> 30) & 0x3;
index = (gva >> 30) & 0x3UL;
entry = base[index];
if ((entry & MMU_32BIT_PDE_P) == 0U) {
@@ -264,7 +264,7 @@ int gva2gpa(struct vcpu *vcpu, uint64_t gva, uint64_t *gpa,
pw_info.level = pm;
pw_info.is_write_access = !!(*err_code & PAGE_FAULT_WR_FLAG);
pw_info.is_inst_fetch = !!(*err_code & PAGE_FAULT_ID_FLAG);
pw_info.is_user_mode = ((exec_vmread(VMX_GUEST_CS_SEL) & 0x3) == 3);
pw_info.is_user_mode = ((exec_vmread(VMX_GUEST_CS_SEL) & 0x3UL) == 3UL);
pw_info.pse = true;
pw_info.nxe = cur_context->ia32_efer & MSR_IA32_EFER_NXE_BIT;
pw_info.wp = !!(cur_context->cr0 & CR0_WP);
@@ -418,7 +418,7 @@ void init_e820(void)
struct multiboot_info *mbi =
(struct multiboot_info *)((uint64_t)boot_regs[1]);
pr_info("Multiboot info detected\n");
if ((mbi->mi_flags & 0x40) != 0U) {
if ((mbi->mi_flags & 0x40U) != 0U) {
struct multiboot_mmap *mmap =
(struct multiboot_mmap *)
((uint64_t)mbi->mi_mmap_addr);

56
hypervisor/arch/x86/guest/instr_emul.c
View File

@@ -55,11 +55,11 @@ enum {
};
/* struct vie_op.op_flags */
#define VIE_OP_F_IMM (1 << 0) /* 16/32-bit immediate operand */
#define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
#define VIE_OP_F_MOFFSET (1 << 2) /* 16/32/64-bit immediate moffset */
#define VIE_OP_F_NO_MODRM (1 << 3)
#define VIE_OP_F_NO_GLA_VERIFICATION (1 << 4)
#define VIE_OP_F_IMM (1U << 0) /* 16/32-bit immediate operand */
#define VIE_OP_F_IMM8 (1U << 1) /* 8-bit immediate operand */
#define VIE_OP_F_MOFFSET (1U << 2) /* 16/32/64-bit immediate moffset */
#define VIE_OP_F_NO_MODRM (1U << 3)
#define VIE_OP_F_NO_GLA_VERIFICATION (1U << 4)
static const struct vie_op two_byte_opcodes[256] = {
[0xB6] = {
@@ -272,9 +272,9 @@ vie_calc_bytereg(struct vie *vie, enum vm_reg_name *reg, int *lhbr)
* %ah, %ch, %dh and %bh respectively.
*/
if (vie->rex_present == 0U) {
if ((vie->reg & 0x4) != 0U) {
if ((vie->reg & 0x4U) != 0U) {
*lhbr = 1;
*reg = gpr_map[vie->reg & 0x3];
*reg = gpr_map[vie->reg & 0x3U];
}
}
}
@@ -1343,7 +1343,7 @@ emulate_push(struct vcpu *vcpu, uint64_t mmio_gpa, struct vie *vie,
* PUSH is part of the group 5 extended opcodes and is identified
* by ModRM:reg = b110.
*/
if ((vie->reg & 7) != 6)
if ((vie->reg & 7U) != 6)
return -EINVAL;
error = emulate_stack_op(vcpu, mmio_gpa, vie, paging, memread,
@@ -1364,7 +1364,7 @@ emulate_pop(struct vcpu *vcpu, uint64_t mmio_gpa, struct vie *vie,
* POP is part of the group 1A extended opcodes and is identified
* by ModRM:reg = b000.
*/
if ((vie->reg & 7) != 0)
if ((vie->reg & 7U) != 0)
return -EINVAL;
error = emulate_stack_op(vcpu, mmio_gpa, vie, paging, memread,
@@ -1380,16 +1380,16 @@ emulate_group1(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
{
int error;
switch (vie->reg & 7) {
case 0x1: /* OR */
switch (vie->reg & 7U) {
case 0x1U: /* OR */
error = emulate_or(vcpu, gpa, vie,
memread, memwrite, memarg);
break;
case 0x4: /* AND */
case 0x4U: /* AND */
error = emulate_and(vcpu, gpa, vie,
memread, memwrite, memarg);
break;
case 0x7: /* CMP */
case 0x7U: /* CMP */
error = emulate_cmp(vcpu, gpa, vie,
memread, memwrite, memarg);
break;
@@ -1415,7 +1415,7 @@ emulate_bittest(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
* Currently we only emulate the 'Bit Test' instruction which is
* identified by a ModR/M:reg encoding of 100b.
*/
if ((vie->reg & 7) != 4)
if ((vie->reg & 7U) != 4)
return -EINVAL;
error = vie_read_register(vcpu, VM_REG_GUEST_RFLAGS, &rflags);
@@ -1607,7 +1607,7 @@ vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
if ((prot & PROT_READ) != 0) {
/* #GP on a read access to a exec-only code segment */
if ((type & 0xA) == 0x8)
if ((type & 0xAU) == 0x8U)
return -1;
}
@@ -1616,10 +1616,10 @@ vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
* #GP on a write access to a code segment or a
* read-only data segment.
*/
if ((type & 0x8) != 0) /* code segment */
if ((type & 0x8U) != 0) /* code segment */
return -1;
if ((type & 0xA) == 0) /* read-only data seg */
if ((type & 0xAU) == 0) /* read-only data seg */
return -1;
}
@@ -1627,7 +1627,7 @@ vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
* 'desc->limit' is fully expanded taking granularity into
* account.
*/
if ((type & 0xC) == 0x4) {
if ((type & 0xCU) == 0x4U) {
/* expand-down data segment */
low_limit = desc->limit + 1;
high_limit = SEG_DESC_DEF32(desc->access) ?
@@ -1786,10 +1786,10 @@ decode_prefixes(struct vie *vie, enum vm_cpu_mode cpu_mode, int cs_d)
*/
if (cpu_mode == CPU_MODE_64BIT && x >= 0x40 && x <= 0x4F) {
vie->rex_present = 1;
vie->rex_w = (x & 0x8) != 0U ? 1 : 0;
vie->rex_r = (x & 0x4) != 0U ? 1 : 0;
vie->rex_x = (x & 0x2) != 0U ? 1 : 0;
vie->rex_b = (x & 0x1) != 0U ? 1 : 0;
vie->rex_w = (x & 0x8U) != 0U ? 1 : 0;
vie->rex_r = (x & 0x4U) != 0U ? 1 : 0;
vie->rex_x = (x & 0x2U) != 0U ? 1 : 0;
vie->rex_b = (x & 0x1U) != 0U ? 1 : 0;
vie_advance(vie);
}
@@ -1872,9 +1872,9 @@ decode_modrm(struct vie *vie, enum vm_cpu_mode cpu_mode)
if (vie_peek(vie, &x) != 0)
return -1;
vie->mod = (x >> 6) & 0x3;
vie->rm = (x >> 0) & 0x7;
vie->reg = (x >> 3) & 0x7;
vie->mod = (x >> 6) & 0x3U;
vie->rm = (x >> 0) & 0x7U;
vie->reg = (x >> 3) & 0x7U;
/*
* A direct addressing mode makes no sense in the context of an EPT
@@ -1954,9 +1954,9 @@ decode_sib(struct vie *vie)
return -1;
/* De-construct the SIB byte */
vie->ss = (x >> 6) & 0x3;
vie->index = (x >> 3) & 0x7;
vie->base = (x >> 0) & 0x7;
vie->ss = (x >> 6) & 0x3U;
vie->index = (x >> 3) & 0x7U;
vie->base = (x >> 0) & 0x7U;
/* Apply the REX prefix modifiers */
vie->index |= vie->rex_x << 3;

2
hypervisor/arch/x86/guest/instr_emul_wrapper.c
View File

@@ -259,7 +259,7 @@ static void get_guest_paging_info(struct vcpu *vcpu, struct emul_cnx *emul_cnx)
ASSERT(emul_cnx != NULL && vcpu != NULL, "Error in input arguments");
csar = exec_vmread(VMX_GUEST_CS_ATTR);
cpl = (csar >> 5) & 3;
cpl = (csar >> 5) & 3U;
emul_cnx->paging.cr3 =
vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context].cr3;
emul_cnx->paging.cpl = cpl;

46
hypervisor/arch/x86/guest/instr_emul_wrapper.h
View File

@@ -79,23 +79,23 @@ struct vie {
struct vie_op op; /* opcode description */
};
#define PSL_C 0x00000001 /* carry bit */
#define PSL_PF 0x00000004 /* parity bit */
#define PSL_AF 0x00000010 /* bcd carry bit */
#define PSL_Z 0x00000040 /* zero bit */
#define PSL_N 0x00000080 /* negative bit */
#define PSL_T 0x00000100 /* trace enable bit */
#define PSL_I 0x00000200 /* interrupt enable bit */
#define PSL_D 0x00000400 /* string instruction direction bit */
#define PSL_V 0x00000800 /* overflow bit */
#define PSL_IOPL 0x00003000 /* i/o privilege level */
#define PSL_NT 0x00004000 /* nested task bit */
#define PSL_RF 0x00010000 /* resume flag bit */
#define PSL_VM 0x00020000 /* virtual 8086 mode bit */
#define PSL_AC 0x00040000 /* alignment checking */
#define PSL_VIF 0x00080000 /* virtual interrupt enable */
#define PSL_VIP 0x00100000 /* virtual interrupt pending */
#define PSL_ID 0x00200000 /* identification bit */
#define PSL_C 0x00000001U /* carry bit */
#define PSL_PF 0x00000004U /* parity bit */
#define PSL_AF 0x00000010U /* bcd carry bit */
#define PSL_Z 0x00000040U /* zero bit */
#define PSL_N 0x00000080U /* negative bit */
#define PSL_T 0x00000100U /* trace enable bit */
#define PSL_I 0x00000200U /* interrupt enable bit */
#define PSL_D 0x00000400U /* string instruction direction bit */
#define PSL_V 0x00000800U /* overflow bit */
#define PSL_IOPL 0x00003000U /* i/o privilege level */
#define PSL_NT 0x00004000U /* nested task bit */
#define PSL_RF 0x00010000U /* resume flag bit */
#define PSL_VM 0x00020000U /* virtual 8086 mode bit */
#define PSL_AC 0x00040000U /* alignment checking */
#define PSL_VIF 0x00080000U /* virtual interrupt enable */
#define PSL_VIP 0x00100000U /* virtual interrupt pending */
#define PSL_ID 0x00200000U /* identification bit */
/*
* The 'access' field has the format specified in Table 21-2 of the Intel
@@ -114,13 +114,13 @@ struct seg_desc {
/*
* Protections are chosen from these bits, or-ed together
*/
#define PROT_NONE 0x00 /* no permissions */
#define PROT_READ 0x01 /* pages can be read */
#define PROT_WRITE 0x02 /* pages can be written */
#define PROT_EXEC 0x04 /* pages can be executed */
#define PROT_NONE 0x00U /* no permissions */
#define PROT_READ 0x01U /* pages can be read */
#define PROT_WRITE 0x02U /* pages can be written */
#define PROT_EXEC 0x04U /* pages can be executed */
#define SEG_DESC_TYPE(access) ((access) & 0x001f)
#define SEG_DESC_DPL(access) (((access) >> 5) & 0x3)
#define SEG_DESC_TYPE(access) ((access) & 0x001fU)
#define SEG_DESC_DPL(access) (((access) >> 5) & 0x3U)
#define SEG_DESC_PRESENT(access) ((((access) & 0x0080U) != 0U) ? 1 : 0)
#define SEG_DESC_DEF32(access) ((((access) & 0x4000U) != 0U) ? 1 : 0)
#define SEG_DESC_GRANULARITY(access) ((((access) & 0x8000U) != 0U) ? 1 : 0)

2
hypervisor/arch/x86/guest/pm.c
View File

@@ -23,7 +23,7 @@ int validate_pstate(struct vm *vm, uint64_t perf_ctl)
}
for (i = 0; i < px_cnt; i++) {
if ((px_data + i)->control == (perf_ctl & 0xffff)) {
if ((px_data + i)->control == (perf_ctl & 0xffffUL)) {
return 0;
}
}

20
hypervisor/arch/x86/interrupt.c
View File

@@ -6,7 +6,7 @@
#include <hypervisor.h>
#define EXCEPTION_ERROR_CODE_VALID 8
#define EXCEPTION_ERROR_CODE_VALID 8U
#define INTERRPUT_QUEUE_BUFF_SIZE 255
#define ACRN_DBG_INTR 6
@@ -140,7 +140,7 @@ static int vcpu_do_pending_event(struct vcpu *vcpu)
}
exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD, VMX_INT_INFO_VALID |
(vector & 0xFF));
(vector & 0xFFU));
vlapic_intr_accepted(vlapic, vector);
return 0;
@@ -162,10 +162,10 @@ static int vcpu_do_pending_extint(struct vcpu *vcpu)
vpic_pending_intr(vcpu->vm, &vector);
if (vector <= NR_MAX_VECTOR) {
dev_dbg(ACRN_DBG_INTR, "VPIC: to inject PIC vector %d\n",
vector & 0xFF);
vector & 0xFFU);
exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD,
VMX_INT_INFO_VALID |
(vector & 0xFF));
(vector & 0xFFU));
vpic_intr_accepted(vcpu->vm, vector);
}
}
@@ -250,7 +250,7 @@ static void _vcpu_inject_exception(struct vcpu *vcpu, uint32_t vector)
}
exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD, VMX_INT_INFO_VALID |
(exception_type[vector] << 8) | (vector & 0xFF));
(exception_type[vector] << 8) | (vector & 0xFFU));
vcpu->arch_vcpu.exception_info.exception = VECTOR_INVALID;
}
@@ -349,7 +349,7 @@ int external_interrupt_vmexit_handler(struct vcpu *vcpu)
return -EINVAL;
}
ctx.vector = intr_info & 0xFF;
ctx.vector = intr_info & 0xFFU;
dispatch_interrupt(&ctx);
@@ -504,7 +504,7 @@ int exception_vmexit_handler(struct vcpu *vcpu)
/* Obtain VM-Exit information field pg 2912 */
intinfo = exec_vmread(VMX_EXIT_INT_INFO);
if ((intinfo & VMX_INT_INFO_VALID) != 0U) {
exception_vector = intinfo & 0xFF;
exception_vector = intinfo & 0xFFU;
/* Check if exception caused by the guest is a HW exception.
* If the exit occurred due to a HW exception obtain the
* error code to be conveyed to get via the stack
@@ -514,12 +514,12 @@ int exception_vmexit_handler(struct vcpu *vcpu)
/* get current privilege level and fault address */
cpl = exec_vmread(VMX_GUEST_CS_ATTR);
cpl = (cpl >> 5) & 3;
cpl = (cpl >> 5) & 3U;
if (cpl < 3)
int_err_code &= ~4;
int_err_code &= ~4U;
else
int_err_code |= 4;
int_err_code |= 4U;
}
}

12
hypervisor/arch/x86/io.c
View File

@@ -165,10 +165,10 @@ void allow_guest_io_access(struct vm *vm, uint32_t address, uint32_t nbytes)
b = vm->arch_vm.iobitmap[0];
for (i = 0; i < nbytes; i++) {
if ((address & 0x8000) != 0U)
if ((address & 0x8000U) != 0U)
b = vm->arch_vm.iobitmap[1];
a = address & 0x7fff;
b[a >> 5] &= ~(1 << (a & 0x1f));
a = address & 0x7fffU;
b[a >> 5] &= ~(1 << (a & 0x1fU));
address++;
}
}
@@ -181,10 +181,10 @@ static void deny_guest_io_access(struct vm *vm, uint32_t address, uint32_t nbyte
b = vm->arch_vm.iobitmap[0];
for (i = 0; i < nbytes; i++) {
if ((address & 0x8000) != 0U)
if ((address & 0x8000U) != 0U)
b = vm->arch_vm.iobitmap[1];
a = address & 0x7fff;
b[a >> 5] |= (1 << (a & 0x1f));
a = address & 0x7fffU;
b[a >> 5] |= (1 << (a & 0x1fU));
address++;
}
}

2
hypervisor/arch/x86/timer.c
View File

@@ -243,7 +243,7 @@ static uint64_t pit_calibrate_tsc(uint16_t cal_ms)
*/
io_write_byte(0x30, 0x43);
io_write_byte(initial_pit & 0x00ff, 0x40); /* Write LSB */
io_write_byte(initial_pit & 0x00ffU, 0x40); /* Write LSB */
io_write_byte(initial_pit >> 8, 0x40); /* Write MSB */
current_tsc = rdtsc();

6
hypervisor/arch/x86/trusty.c
View File

@@ -284,10 +284,10 @@ void switch_world(struct vcpu *vcpu, int next_world)
/* load EPTP for next world */
if (next_world == NORMAL_WORLD) {
exec_vmwrite64(VMX_EPT_POINTER_FULL,
vcpu->vm->arch_vm.nworld_eptp | (3<<3) | 6);
vcpu->vm->arch_vm.nworld_eptp | (3UL<<3) | 6UL);
} else {
exec_vmwrite64(VMX_EPT_POINTER_FULL,
vcpu->vm->arch_vm.sworld_eptp | (3<<3) | 6);
vcpu->vm->arch_vm.sworld_eptp | (3UL<<3) | 6UL);
}
/* Update world index */
@@ -420,7 +420,7 @@ bool initialize_trusty(struct vcpu *vcpu, uint64_t param)
trusty_base_hpa = vm->sworld_control.sworld_memory.base_hpa;
exec_vmwrite64(VMX_EPT_POINTER_FULL,
vm->arch_vm.sworld_eptp | (3<<3) | 6);
vm->arch_vm.sworld_eptp | (3UL<<3) | 6UL);
/* save Normal World context */
save_world_ctx(&vcpu->arch_vcpu.contexts[NORMAL_WORLD]);

8
hypervisor/arch/x86/vmexit.c
View File

@@ -145,7 +145,7 @@ int vmexit_handler(struct vcpu *vcpu)
/* Filter out HW exception & NMI */
if ((vcpu->arch_vcpu.idt_vectoring_info & VMX_INT_INFO_VALID) != 0U) {
uint32_t vector_info = vcpu->arch_vcpu.idt_vectoring_info;
uint32_t vector = vector_info & 0xff;
uint32_t vector = vector_info & 0xffU;
uint32_t type = (vector_info & VMX_INT_TYPE_MASK) >> 8;
uint32_t err_code = 0;
@@ -161,7 +161,7 @@ int vmexit_handler(struct vcpu *vcpu)
}
/* Calculate basic exit reason (low 16-bits) */
basic_exit_reason = vcpu->arch_vcpu.exit_reason & 0xFFFF;
basic_exit_reason = vcpu->arch_vcpu.exit_reason & 0xFFFFU;
/* Log details for exit */
pr_dbg("Exit Reason: 0x%016llx ", vcpu->arch_vcpu.exit_reason);
@@ -327,7 +327,7 @@ static int xsetbv_vmexit_handler(struct vcpu *vcpu)
(ctx_ptr->guest_cpu_regs.regs.rdx << 32);
/*bit 0(x87 state) of XCR0 can't be cleared*/
if ((val64 & 0x01) == 0U) {
if ((val64 & 0x01UL) == 0U) {
vcpu_inject_gp(vcpu, 0);
return -1;
}
@@ -336,7 +336,7 @@ static int xsetbv_vmexit_handler(struct vcpu *vcpu)
*set to 10b as it is necessary to set both bits
*to use AVX instructions.
**/
if (((val64 >> 1) & 0x3) == 0x2) {
if (((val64 >> 1) & 0x3UL) == 0x2UL) {
vcpu_inject_gp(vcpu, 0);
return -1;
}