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hv:fix MISRA-C violation in virq.c

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The MISRA-C Standards suggests procedures to be single exit

Tracked-On: #861
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
This commit is contained in:
yuhong.tao@intel.com 2019-01-16 20:12:34 +08:00 committed by wenlingz
parent 6641bc7949
commit ae144e1a56
1 changed files with 40 additions and 34 deletions
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26
hypervisor/arch/x86/virq.c
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@ -177,14 +177,18 @@ static int32_t vcpu_do_pending_extint(const struct acrn_vcpu *vcpu)
/* SDM Vol3 -6.15, Table 6-4 - interrupt and exception classes */ /* SDM Vol3 -6.15, Table 6-4 - interrupt and exception classes */
static int32_t get_excep_class(uint32_t vector) static int32_t get_excep_class(uint32_t vector)
{ {
int32_t ret;
if ((vector == IDT_DE) || (vector == IDT_TS) || (vector == IDT_NP) || if ((vector == IDT_DE) || (vector == IDT_TS) || (vector == IDT_NP) ||
(vector == IDT_SS) || (vector == IDT_GP)) { (vector == IDT_SS) || (vector == IDT_GP)) {
return EXCEPTION_CLASS_CONT; ret = EXCEPTION_CLASS_CONT;
} else if ((vector == IDT_PF) || (vector == IDT_VE)) { } else if ((vector == IDT_PF) || (vector == IDT_VE)) {
return EXCEPTION_CLASS_PF; ret = EXCEPTION_CLASS_PF;
} else { } else {
return EXCEPTION_CLASS_BENIGN; ret = EXCEPTION_CLASS_BENIGN;
} }
return ret;
} }
int32_t vcpu_queue_exception(struct acrn_vcpu *vcpu, uint32_t vector_arg, uint32_t err_code_arg) int32_t vcpu_queue_exception(struct acrn_vcpu *vcpu, uint32_t vector_arg, uint32_t err_code_arg)
@ -192,15 +196,15 @@ int32_t vcpu_queue_exception(struct acrn_vcpu *vcpu, uint32_t vector_arg, uint32
struct acrn_vcpu_arch *arch = &vcpu->arch; struct acrn_vcpu_arch *arch = &vcpu->arch;
uint32_t vector = vector_arg; uint32_t vector = vector_arg;
uint32_t err_code = err_code_arg; uint32_t err_code = err_code_arg;
int32_t ret = 0;
/* VECTOR_INVALID is also greater than 32 */ /* VECTOR_INVALID is also greater than 32 */
if (vector >= 32U) { if (vector >= 32U) {
pr_err("invalid exception vector %d", vector); pr_err("invalid exception vector %d", vector);
return -EINVAL; ret = -EINVAL;
} } else {
uint32_t prev_vector = uint32_t prev_vector = arch->exception_info.exception;
arch->exception_info.exception;
int32_t new_class, prev_class; int32_t new_class, prev_class;
/* SDM vol3 - 6.15, Table 6-5 - conditions for generating a /* SDM vol3 - 6.15, Table 6-5 - conditions for generating a
@ -210,8 +214,8 @@ int32_t vcpu_queue_exception(struct acrn_vcpu *vcpu, uint32_t vector_arg, uint32
if ((prev_vector == IDT_DF) && (new_class != EXCEPTION_CLASS_BENIGN)) { if ((prev_vector == IDT_DF) && (new_class != EXCEPTION_CLASS_BENIGN)) {
/* triple fault happen - shutdwon mode */ /* triple fault happen - shutdwon mode */
vcpu_make_request(vcpu, ACRN_REQUEST_TRP_FAULT); vcpu_make_request(vcpu, ACRN_REQUEST_TRP_FAULT);
return 0; } else {
} else if (((prev_class == EXCEPTION_CLASS_CONT) && (new_class == EXCEPTION_CLASS_CONT)) || if (((prev_class == EXCEPTION_CLASS_CONT) && (new_class == EXCEPTION_CLASS_CONT)) ||
((prev_class == EXCEPTION_CLASS_PF) && (new_class != EXCEPTION_CLASS_BENIGN))) { ((prev_class == EXCEPTION_CLASS_PF) && (new_class != EXCEPTION_CLASS_BENIGN))) {
/* generate double fault */ /* generate double fault */
vector = IDT_DF; vector = IDT_DF;
@ -228,8 +232,10 @@ int32_t vcpu_queue_exception(struct acrn_vcpu *vcpu, uint32_t vector_arg, uint32
} else { } else {
arch->exception_info.error = 0U; arch->exception_info.error = 0U;
} }
}
}
return 0; return ret;
} }
static void vcpu_inject_exception(struct acrn_vcpu *vcpu, uint32_t vector) static void vcpu_inject_exception(struct acrn_vcpu *vcpu, uint32_t vector)