mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-18 11:47:30 +00:00
hv:Reshuffle console/uart code
The current hierarchy : CONSOLE --> SERIAL -->UART DRIVER This patch remove SERIAL layer, that is console will call UART driver directly, change it to: CONSOLE --> UART DRIVER Remove some related data structures and registration and callback. Cleanup vuart.c Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
parent
b7436272e7
commit
ae3004028b
@ -478,9 +478,6 @@ static void bsp_boot_post(void)
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/* Perform any necessary BSP initialization */
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/* Perform any necessary BSP initialization */
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init_bsp();
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init_bsp();
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/* Initialize Serial */
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serial_init();
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/* Initialize console */
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/* Initialize console */
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console_init();
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console_init();
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@ -5,169 +5,52 @@
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*/
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*/
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#include <hypervisor.h>
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#include <hypervisor.h>
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#include "serial_internal.h"
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#include "uart16550.h"
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static spinlock_t lock;
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static uint32_t serial_handle = SERIAL_INVALID_HANDLE;
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struct hv_timer console_timer;
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struct hv_timer console_timer;
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#define CONSOLE_KICK_TIMER_TIMEOUT 40 /* timeout is 40ms*/
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#define CONSOLE_KICK_TIMER_TIMEOUT 40 /* timeout is 40ms*/
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uint32_t get_serial_handle(void)
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{
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return serial_handle;
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}
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static void print_char(char x)
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{
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(void)serial_puts(serial_handle, &x, 1);
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if (x == '\n') {
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(void)serial_puts(serial_handle, "\r", 1);
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}
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}
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void console_init(void)
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void console_init(void)
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{
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{
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spinlock_init(&lock);
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uart16550_init();
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serial_handle = serial_open("STDIO");
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}
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}
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int console_putc(int ch)
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void console_putc(const char *ch)
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{
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{
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int res = -1;
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(void)uart16550_puts(ch, 1);
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spinlock_obtain(&lock);
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if (serial_handle != SERIAL_INVALID_HANDLE) {
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print_char(ch);
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res = 0;
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}
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spinlock_release(&lock);
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return res;
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}
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}
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int console_puts(const char *s_arg)
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int console_write(const char *s, size_t len)
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{
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{
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const char *s = s_arg;
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return uart16550_puts(s, len);
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int res = -1;
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const char *p;
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spinlock_obtain(&lock);
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if (serial_handle != SERIAL_INVALID_HANDLE) {
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res = 0;
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while ((*s) != 0) {
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/* start output at the beginning of the string search
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* for end of string or '\n'
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*/
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p = s;
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while ((*p != 0) && *p != '\n') {
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++p;
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}
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/* write all characters up to p */
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(void)serial_puts(serial_handle, s, p - s);
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res += p - s;
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if (*p == '\n') {
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print_char('\n');
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++p;
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res += 2;
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}
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/* continue at position p */
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s = p;
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}
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}
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spinlock_release(&lock);
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return res;
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}
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}
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int console_write(const char *s_arg, size_t len)
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char console_getc(void)
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{
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{
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const char *s = s_arg;
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return uart16550_getc();
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int res = -1;
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const char *e;
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const char *p;
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spinlock_obtain(&lock);
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if (serial_handle != SERIAL_INVALID_HANDLE) {
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/* calculate pointer to the end of the string */
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e = s + len;
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res = 0;
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/* process all characters */
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while (s != e) {
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/* search for '\n' or the end of the string */
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p = s;
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while ((p != e) && (*p != '\n')) {
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++p;
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}
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/* write all characters processed so far */
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(void)serial_puts(serial_handle, s, p - s);
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res += p - s;
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/* write '\n' if end of string is not reached */
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if (p != e) {
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print_char('\n');
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++p;
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res += 2;
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}
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/* continue at next position */
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s = p;
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}
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}
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spinlock_release(&lock);
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return res;
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}
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static void console_read(void)
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{
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spinlock_obtain(&lock);
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if (serial_handle != SERIAL_INVALID_HANDLE) {
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/* Get all the data available in the RX FIFO */
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(void)serial_get_rx_data(serial_handle);
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}
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spinlock_release(&lock);
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}
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}
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static void console_handler(void)
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static void console_handler(void)
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{
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{
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/* Dump the RX FIFO to a circular buffer */
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struct vuart *vu;
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console_read();
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/* serial Console Rx operation */
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vu = vuart_console_active();
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vuart_console_rx_chars(serial_handle);
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if (vu != NULL) {
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/* serial Console Rx operation */
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/* serial Console Tx operation */
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vuart_console_rx_chars(vu);
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vuart_console_tx_chars();
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/* serial Console Tx operation */
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vuart_console_tx_chars(vu);
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shell_kick_session();
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} else {
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shell_kick_session();
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}
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}
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}
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static int console_timer_callback(__unused void *data)
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static int console_timer_callback(__unused void *data)
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{
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{
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/* Kick HV-Shell and Uart-Console tasks */
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/* Kick HV-Shell and Uart-Console tasks */
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console_handler();
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console_handler();
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return 0;
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return 0;
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}
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}
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@ -175,12 +58,6 @@ void console_setup_timer(void)
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{
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{
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uint64_t period_in_cycle, fire_tsc;
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uint64_t period_in_cycle, fire_tsc;
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if (serial_handle == SERIAL_INVALID_HANDLE) {
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pr_err("%s: no uart, not need setup console timer",
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__func__);
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return;
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}
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period_in_cycle = CYCLES_PER_MS * CONSOLE_KICK_TIMER_TIMEOUT;
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period_in_cycle = CYCLES_PER_MS * CONSOLE_KICK_TIMER_TIMEOUT;
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fire_tsc = rdtsc() + period_in_cycle;
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fire_tsc = rdtsc() + period_in_cycle;
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initialize_timer(&console_timer,
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initialize_timer(&console_timer,
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@ -23,10 +23,10 @@ static int charout(int cmd, const char *s_arg, uint32_t sz_arg, void *hnd)
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*nchars += (s - p);
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*nchars += (s - p);
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} else {
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} else {
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/* fill mode */
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/* fill mode */
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*nchars += sz;
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*nchars += sz;
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while (sz != 0U) {
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while (sz != 0U) {
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(void)console_putc(*s);
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console_putc(s);
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sz--;
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sz--;
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}
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}
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}
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}
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@ -7,7 +7,6 @@
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#include <hypervisor.h>
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#include <hypervisor.h>
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#include <reboot.h>
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#include <reboot.h>
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#include "shell_internal.h"
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#include "shell_internal.h"
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#include "serial_internal.h"
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#define TEMP_STR_SIZE 60
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#define TEMP_STR_SIZE 60
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#define MAX_STR_SIZE 256
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#define MAX_STR_SIZE 256
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@ -350,27 +349,13 @@ int shell_process_cmd(struct shell *p_shell, char *p_input_line)
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return status;
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return status;
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}
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}
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int shell_init_serial(struct shell *p_shell)
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void shell_init_serial(struct shell *p_shell)
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{
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{
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int status = 0;
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shell_set_name(p_shell, "Serial");
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uint32_t serial_handle = get_serial_handle();
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if (serial_handle != SERIAL_INVALID_HANDLE) {
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p_shell->session_io.io_session_info =
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(void *)(uint64_t)serial_handle;
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status = shell_set_name(p_shell, "Serial");
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} else {
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status = NO_SERIAL_SHELL;
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pr_err("Error: Unable to get a valid serial port handle");
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}
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/* Zero fill the input buffer */
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/* Zero fill the input buffer */
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(void)memset((void *)p_shell->input_line[p_shell->input_line_active], 0,
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(void)memset((void *)p_shell->input_line[p_shell->input_line_active], 0,
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SHELL_CMD_MAX_LEN + 1U);
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SHELL_CMD_MAX_LEN + 1U);
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return status;
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}
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}
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#define SHELL_ROWS 10
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#define SHELL_ROWS 10
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@ -1122,30 +1107,20 @@ int shell_trigger_crash(struct shell *p_shell, int argc, char **argv)
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return 0;
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return 0;
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}
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}
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int shell_terminate_serial(struct shell *p_shell)
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void shell_terminate_serial(__unused struct shell *p_shell)
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{
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{
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/* Shell shouldn't own the serial port handle anymore. */
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p_shell->session_io.io_session_info = NULL;
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return 0;
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}
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}
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void shell_puts_serial(struct shell *p_shell, char *string_ptr)
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void shell_puts_serial(__unused struct shell *p_shell, const char *string_ptr)
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{
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{
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uint32_t serial_handle =
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(uint32_t)(uint64_t)p_shell->session_io.io_session_info;
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/* Output the string */
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/* Output the string */
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(void)serial_puts(serial_handle, string_ptr,
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(void)console_write(string_ptr, strnlen_s(string_ptr,
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strnlen_s(string_ptr, SHELL_STRING_MAX_LEN));
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SHELL_STRING_MAX_LEN));
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}
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}
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uint8_t shell_getc_serial(struct shell *p_shell)
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char shell_getc_serial(__unused struct shell *p_shell)
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{
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{
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uint32_t serial_handle =
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return console_getc();
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(uint32_t)(uint64_t)p_shell->session_io.io_session_info;
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return serial_getc(serial_handle);
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}
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}
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void shell_special_serial(struct shell *p_shell, uint8_t ch)
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void shell_special_serial(struct shell *p_shell, uint8_t ch)
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@ -13,11 +13,10 @@ struct shell;
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/* Structure to hold the details about shell input and output */
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/* Structure to hold the details about shell input and output */
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struct shell_io {
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struct shell_io {
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void *io_session_info;
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void (*io_init)(struct shell *);
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int (*io_init)(struct shell *);
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void (*io_deinit)(struct shell *);
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int (*io_deinit)(struct shell *);
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void (*io_puts)(struct shell *, const char *);
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void (*io_puts)(struct shell *, char *);
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char (*io_getc)(struct shell *);
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uint8_t (*io_getc)(struct shell *);
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void (*io_special)(struct shell *, uint8_t);
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void (*io_special)(struct shell *, uint8_t);
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bool io_echo_on;
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bool io_echo_on;
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};
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};
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@ -159,15 +158,15 @@ int shell_set_loglevel(struct shell *p_shell, int argc, char **argv);
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int shell_cpuid(struct shell *p_shell, int argc, char **argv);
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int shell_cpuid(struct shell *p_shell, int argc, char **argv);
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struct shell_cmd *shell_find_cmd(struct shell *p_shell, const char *cmd);
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struct shell_cmd *shell_find_cmd(struct shell *p_shell, const char *cmd);
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int shell_process_cmd(struct shell *p_shell, char *p_input_line);
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int shell_process_cmd(struct shell *p_shell, char *p_input_line);
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int shell_terminate_serial(struct shell *p_shell);
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void shell_terminate_serial(struct shell *p_shell);
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int shell_init_serial(struct shell *p_shell);
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void shell_init_serial(struct shell *p_shell);
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void shell_puts_serial(struct shell *p_shell, char *string_ptr);
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void shell_puts_serial(struct shell *p_shell, const char *string_ptr);
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uint8_t shell_getc_serial(struct shell *p_shell);
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char shell_getc_serial(struct shell *p_shell);
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void shell_special_serial(struct shell *p_shell, uint8_t ch);
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void shell_special_serial(struct shell *p_shell, uint8_t ch);
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void kick_shell(struct shell *p_shell);
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void kick_shell(struct shell *p_shell);
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void shell_puts(struct shell *p_shell, const char *str_ptr);
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void shell_puts(struct shell *p_shell, const char *str_ptr);
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int shell_set_name(struct shell *p_shell, const char *name);
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void shell_set_name(struct shell *p_shell, const char *name);
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int shell_trigger_crash(struct shell *p_shell, int argc, char **argv);
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int shell_trigger_crash(struct shell *p_shell, int argc, char **argv);
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#endif /* SHELL_INTER_H */
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#endif /* SHELL_INTER_H */
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{
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{
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/* Transmit data using this shell session's 'puts' function */
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/* Transmit data using this shell session's 'puts' function */
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p_shell->session_io.io_puts(p_shell, str_ptr);
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p_shell->session_io.io_puts(p_shell, str_ptr);
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}
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}
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int shell_set_name(struct shell *p_shell, const char *name)
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/**
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* @pre p_shell != NULL
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* @pre name != NULL
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*/
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void shell_set_name(struct shell *p_shell, const char *name)
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{
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{
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int status;
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(void)strncpy_s((void *) p_shell->name, SHELL_NAME_MAX_LEN,
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(void *) name, SHELL_NAME_MAX_LEN - 1);
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if ((p_shell != NULL) && (name != NULL)) {
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/* Ensure null terminated string */
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(void)strncpy_s((void *) p_shell->name, SHELL_NAME_MAX_LEN,
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p_shell->name[SHELL_NAME_MAX_LEN - 1] = 0;
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(void *) name, SHELL_NAME_MAX_LEN - 1);
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/* Ensure null terminated string */
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p_shell->name[SHELL_NAME_MAX_LEN - 1] = 0;
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status = 0;
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} else {
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status = -EINVAL;
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}
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return status;
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}
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}
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void shell_kick_session(void)
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void shell_kick_session(void)
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@ -6,13 +6,6 @@
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#include <hypervisor.h>
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#include <hypervisor.h>
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#include "uart16550.h"
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#include "uart16550.h"
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#include "serial_internal.h"
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/* Mapping of 16c550 write-only registers to appropriate structure members */
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#define THR_IDX RBR_IDX
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#define IIR_IDX FCR_IDX
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#define DLL_IDX RBR_IDX
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#define DLM_IDX IER_IDX
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#if defined(CONFIG_SERIAL_PIO_BASE)
|
#if defined(CONFIG_SERIAL_PIO_BASE)
|
||||||
static int serial_port_mapped = 1;
|
static int serial_port_mapped = 1;
|
||||||
@ -31,35 +24,10 @@ static int uart_enabled;
|
|||||||
|
|
||||||
typedef uint32_t uart_reg_t;
|
typedef uint32_t uart_reg_t;
|
||||||
|
|
||||||
enum UART_REG_IDX{
|
static uint64_t uart_base_address;
|
||||||
RBR_IDX, /* 0 */
|
|
||||||
IER_IDX, /* 1 */
|
|
||||||
FCR_IDX, /* 2 */
|
|
||||||
LCR_IDX, /* 3 */
|
|
||||||
MCR_IDX, /* 4 */
|
|
||||||
ISR_IDX, /* 5 */
|
|
||||||
MSR_IDX, /* 6 */
|
|
||||||
SPR_IDX, /* 7 */
|
|
||||||
MDR1_IDX, /* 8 */
|
|
||||||
REG9_IDX, /* 9 */
|
|
||||||
REGA_IDX, /* A */
|
|
||||||
REGB_IDX, /* B */
|
|
||||||
REGC_IDX, /* C */
|
|
||||||
REGD_IDX, /* D */
|
|
||||||
REGE_IDX, /* E */
|
|
||||||
UASR_IDX, /* F */
|
|
||||||
SCR_IDX, /* 10*/
|
|
||||||
SSR_IDX, /* 11*/
|
|
||||||
REG12_IDX, /* 12*/
|
|
||||||
OSC_12M_SEL_IDX, /* 13*/
|
|
||||||
};
|
|
||||||
|
|
||||||
/* CPU oscillator clock */
|
static spinlock_t uart_rx_lock;
|
||||||
#define CPU_OSC_CLOCK 1843200 /* 1.8432 MHz */
|
static spinlock_t uart_tx_lock;
|
||||||
|
|
||||||
/* UART hardware definitions */
|
|
||||||
#define UART_CLOCK_RATE CPU_OSC_CLOCK
|
|
||||||
#define UART_BUFFER_SIZE 2048
|
|
||||||
|
|
||||||
static inline uint32_t uart16550_read_reg(uint64_t base, uint32_t reg_idx)
|
static inline uint32_t uart16550_read_reg(uint64_t base, uint32_t reg_idx)
|
||||||
{
|
{
|
||||||
@ -80,12 +48,8 @@ static inline void uart16550_write_reg(uint64_t base,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void uart16550_enable(__unused struct tgt_uart *tgt_uart)
|
static void uart16550_calc_baud_div(uint32_t ref_freq,
|
||||||
{
|
uint32_t *baud_div_ptr, uint32_t baud_rate_arg)
|
||||||
}
|
|
||||||
|
|
||||||
static void uart16550_calc_baud_div(__unused struct tgt_uart *tgt_uart,
|
|
||||||
uint32_t ref_freq, uint32_t *baud_div_ptr, uint32_t baud_rate_arg)
|
|
||||||
{
|
{
|
||||||
uint32_t baud_rate = baud_rate_arg;
|
uint32_t baud_rate = baud_rate_arg;
|
||||||
uint32_t baud_multiplier = baud_rate < BAUD_460800 ? 16 : 13;
|
uint32_t baud_multiplier = baud_rate < BAUD_460800 ? 16 : 13;
|
||||||
@ -96,223 +60,108 @@ static void uart16550_calc_baud_div(__unused struct tgt_uart *tgt_uart,
|
|||||||
*baud_div_ptr = ref_freq / (baud_multiplier * baud_rate);
|
*baud_div_ptr = ref_freq / (baud_multiplier * baud_rate);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void uart16550_set_baud_rate(struct tgt_uart *tgt_uart,
|
static void uart16550_set_baud_rate(uint32_t baud_rate)
|
||||||
uint32_t baud_rate)
|
|
||||||
{
|
{
|
||||||
uint32_t baud_div, duart_clock = CPU_OSC_CLOCK;
|
uint32_t baud_div, duart_clock = UART_CLOCK_RATE;
|
||||||
uart_reg_t temp_reg;
|
uart_reg_t temp_reg;
|
||||||
|
|
||||||
/* Calculate baud divisor */
|
/* Calculate baud divisor */
|
||||||
uart16550_calc_baud_div(
|
uart16550_calc_baud_div(duart_clock, &baud_div, baud_rate);
|
||||||
tgt_uart, duart_clock, &baud_div, baud_rate);
|
|
||||||
|
|
||||||
/* Enable DLL and DLM registers for setting the Divisor */
|
/* Enable DLL and DLM registers for setting the Divisor */
|
||||||
temp_reg = uart16550_read_reg(tgt_uart->base_address, LCR_IDX);
|
temp_reg = uart16550_read_reg(uart_base_address, UART16550_LCR);
|
||||||
temp_reg |= LCR_DLAB;
|
temp_reg |= LCR_DLAB;
|
||||||
uart16550_write_reg(tgt_uart->base_address, temp_reg, LCR_IDX);
|
uart16550_write_reg(uart_base_address, temp_reg, UART16550_LCR);
|
||||||
|
|
||||||
/* Write the appropriate divisor value */
|
/* Write the appropriate divisor value */
|
||||||
uart16550_write_reg(tgt_uart->base_address,
|
uart16550_write_reg(uart_base_address,
|
||||||
((baud_div >> 8) & 0xFFU), DLM_IDX);
|
((baud_div >> 8) & 0xFFU), UART16550_DLM);
|
||||||
uart16550_write_reg(tgt_uart->base_address,
|
uart16550_write_reg(uart_base_address,
|
||||||
(baud_div & 0xFFU), DLL_IDX);
|
(baud_div & 0xFFU), UART16550_DLL);
|
||||||
|
|
||||||
/* Disable DLL and DLM registers */
|
/* Disable DLL and DLM registers */
|
||||||
temp_reg &= ~LCR_DLAB;
|
temp_reg &= ~LCR_DLAB;
|
||||||
uart16550_write_reg(tgt_uart->base_address, temp_reg, LCR_IDX);
|
uart16550_write_reg(uart_base_address, temp_reg, UART16550_LCR);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int uart16550_init(struct tgt_uart *tgt_uart)
|
void uart16550_init(void)
|
||||||
{
|
{
|
||||||
int status = 0;
|
if (uart_base_address == 0) {
|
||||||
|
uart_base_address = UART_BASE_ADDRESS;
|
||||||
if (uart_enabled == 0) {
|
|
||||||
/*uart will not be used */
|
|
||||||
status = -ENODEV;
|
|
||||||
} else {
|
|
||||||
if (strcmp(tgt_uart->uart_id, "STDIO") == 0) {
|
|
||||||
atomic_store32(&tgt_uart->open_count, 0U);
|
|
||||||
} else {
|
|
||||||
/* set open count to 1 to prevent open */
|
|
||||||
atomic_store32(&tgt_uart->open_count, 1U);
|
|
||||||
status = -EINVAL;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
spinlock_init(&uart_rx_lock);
|
||||||
|
spinlock_init(&uart_tx_lock);
|
||||||
|
/* Enable TX and RX FIFOs */
|
||||||
|
uart16550_write_reg(uart_base_address,
|
||||||
|
FCR_FIFOE | FCR_RFR | FCR_TFR, UART16550_FCR);
|
||||||
|
|
||||||
return status;
|
/* Set-up data bits / parity / stop bits. */
|
||||||
|
uart16550_write_reg(uart_base_address,
|
||||||
|
(LCR_WL8 | LCR_NB_STOP_BITS_1 | LCR_PARITY_NONE),
|
||||||
|
UART16550_LCR);
|
||||||
|
|
||||||
|
/* Disable interrupts (we use polling) */
|
||||||
|
uart16550_write_reg(uart_base_address,
|
||||||
|
UART_IER_DISABLE_ALL, UART16550_IER);
|
||||||
|
|
||||||
|
/* Set baud rate */
|
||||||
|
uart16550_set_baud_rate(BAUD_115200);
|
||||||
|
|
||||||
|
/* Data terminal ready + Request to send */
|
||||||
|
uart16550_write_reg(uart_base_address,
|
||||||
|
MCR_RTS | MCR_DTR, UART16550_MCR);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int uart16550_open(struct tgt_uart *tgt_uart,
|
char uart16550_getc(void)
|
||||||
struct uart_config *config)
|
|
||||||
{
|
{
|
||||||
uint32_t temp32;
|
char ret = -1;
|
||||||
int status = 0;
|
|
||||||
|
|
||||||
if (strcmp(tgt_uart->uart_id, "STDIO") == 0) {
|
spinlock_obtain(&uart_rx_lock);
|
||||||
if (atomic_cmpxchg32(&tgt_uart->open_count, 0U, 1U) != 0U) {
|
|
||||||
return -EBUSY;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Call UART setup function */
|
|
||||||
/* Enable TX and RX FIFOs */
|
|
||||||
uart16550_write_reg(tgt_uart->base_address,
|
|
||||||
FCR_FIFOE | FCR_RFR | FCR_TFR, FCR_IDX);
|
|
||||||
|
|
||||||
/* Set parity value */
|
|
||||||
if (config->parity_bits == PARITY_ODD) {
|
|
||||||
/* Odd parity */
|
|
||||||
temp32 = LCR_PARITY_ODD;
|
|
||||||
} else if (config->parity_bits == PARITY_EVEN) {
|
|
||||||
/* Even parity */
|
|
||||||
temp32 = LCR_PARITY_EVEN;
|
|
||||||
} else {
|
|
||||||
/* No parity */
|
|
||||||
temp32 = LCR_PARITY_NONE;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set Data length */
|
|
||||||
if (config->data_bits == DATA_7) {
|
|
||||||
/* Set bits for 7 data bits */
|
|
||||||
temp32 |= LCR_WL7;
|
|
||||||
} else {
|
|
||||||
/* Set bits for 8 data bits */
|
|
||||||
temp32 |= LCR_WL8;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Check for 1 stop bit */
|
|
||||||
if (config->stop_bits == STOP_1) {
|
|
||||||
/* Set bits for 1 stop bit */
|
|
||||||
temp32 |= LCR_NB_STOP_BITS_1;
|
|
||||||
} else {
|
|
||||||
/* Set bits for 2 stop bits */
|
|
||||||
temp32 |= LCR_NB_STOP_BITS_2;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set-up data bits / parity / stop bits. */
|
|
||||||
uart16550_write_reg(tgt_uart->base_address,
|
|
||||||
temp32, LCR_IDX);
|
|
||||||
|
|
||||||
/* Disable interrupts (we use polling) */
|
|
||||||
uart16550_write_reg(tgt_uart->base_address,
|
|
||||||
UART_IER_DISABLE_ALL, IER_IDX);
|
|
||||||
|
|
||||||
/* Set baud rate */
|
|
||||||
uart16550_set_baud_rate(tgt_uart, config->baud_rate);
|
|
||||||
|
|
||||||
/* Data terminal ready + Request to send */
|
|
||||||
uart16550_write_reg(tgt_uart->base_address,
|
|
||||||
MCR_RTS | MCR_DTR, MCR_IDX);
|
|
||||||
|
|
||||||
/* Enable the UART hardware */
|
|
||||||
uart16550_enable(tgt_uart);
|
|
||||||
} else {
|
|
||||||
status = -ENODEV;
|
|
||||||
}
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
static uint32_t uart16550_get_rx_err(uint32_t rx_data)
|
|
||||||
{
|
|
||||||
uint32_t rx_status = SD_RX_NO_ERROR;
|
|
||||||
|
|
||||||
/* Check for RX overrun error */
|
|
||||||
if ((rx_data & LSR_OE) != 0U) {
|
|
||||||
rx_status |= SD_RX_OVERRUN_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Check for RX parity error */
|
|
||||||
if ((rx_data & LSR_PE) != 0U) {
|
|
||||||
rx_status |= SD_RX_PARITY_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Check for RX frame error */
|
|
||||||
if ((rx_data & LSR_FE) != 0U) {
|
|
||||||
rx_status |= SD_RX_FRAME_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Return the rx status */
|
|
||||||
return rx_status;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void uart16550_close(struct tgt_uart *tgt_uart)
|
|
||||||
{
|
|
||||||
if (tgt_uart != NULL) {
|
|
||||||
if (atomic_cmpxchg32(&tgt_uart->open_count, 1U, 0U) == 1U) {
|
|
||||||
/* TODO: Add logic to disable the UART */
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void uart16550_read(struct tgt_uart *tgt_uart, void *buffer,
|
|
||||||
uint32_t *bytes_read)
|
|
||||||
{
|
|
||||||
/* If a character has been received, read it */
|
/* If a character has been received, read it */
|
||||||
if ((uart16550_read_reg(tgt_uart->base_address, ISR_IDX) & LSR_DR)
|
if ((uart16550_read_reg(uart_base_address, UART16550_LSR) & LSR_DR)
|
||||||
== LSR_DR) {
|
== LSR_DR) {
|
||||||
/* Read a character */
|
/* Read a character */
|
||||||
*(uint8_t *)buffer =
|
ret = uart16550_read_reg(uart_base_address, UART16550_RBR);
|
||||||
uart16550_read_reg(tgt_uart->base_address, RBR_IDX);
|
|
||||||
|
|
||||||
/* Read 1 byte */
|
|
||||||
*bytes_read = 1U;
|
|
||||||
} else {
|
|
||||||
*bytes_read = 0U;
|
|
||||||
}
|
}
|
||||||
|
spinlock_release(&uart_rx_lock);
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void uart16550_write(struct tgt_uart *tgt_uart,
|
static void uart16550_putc(const char *buf)
|
||||||
const void *buffer, uint32_t *bytes_written)
|
|
||||||
{
|
{
|
||||||
|
uint32_t reg;
|
||||||
/* Ensure there are no further Transmit buffer write requests */
|
/* Ensure there are no further Transmit buffer write requests */
|
||||||
do {
|
do {
|
||||||
} while ((uart16550_read_reg(tgt_uart->base_address,
|
reg = uart16550_read_reg(uart_base_address, UART16550_LSR);
|
||||||
ISR_IDX) & LSR_THRE) == 0U);
|
} while ((reg & LSR_THRE) == 0U || (reg & LSR_TEMT) == 0U);
|
||||||
|
|
||||||
/* Transmit the character. */
|
/* Transmit the character. */
|
||||||
uart16550_write_reg(tgt_uart->base_address,
|
uart16550_write_reg(uart_base_address, *buf, UART16550_THR);
|
||||||
*(uint8_t *)buffer, THR_IDX);
|
|
||||||
|
|
||||||
if (bytes_written != NULL) {
|
|
||||||
*bytes_written = 1;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool uart16550_tx_is_busy(struct tgt_uart *tgt_uart)
|
int uart16550_puts(const char *buf, uint32_t len)
|
||||||
{
|
{
|
||||||
return ((uart16550_read_reg(tgt_uart->base_address, ISR_IDX) &
|
uint32_t i;
|
||||||
(LSR_TEMT)) == 0) ? true : false;
|
|
||||||
}
|
|
||||||
|
|
||||||
static bool uart16550_rx_data_is_avail(struct tgt_uart *tgt_uart,
|
|
||||||
uint32_t *lsr_reg)
|
|
||||||
{
|
|
||||||
*(uart_reg_t *)lsr_reg =
|
|
||||||
uart16550_read_reg(tgt_uart->base_address, ISR_IDX);
|
|
||||||
return ((*(uart_reg_t *)lsr_reg & LSR_DR) == LSR_DR) ? true : false;
|
|
||||||
}
|
|
||||||
|
|
||||||
struct tgt_uart Tgt_Uarts[SERIAL_MAX_DEVS] = {
|
|
||||||
{
|
|
||||||
.uart_id = "STDIO",
|
|
||||||
.base_address = UART_BASE_ADDRESS,
|
|
||||||
.clock_frequency = UART_CLOCK_RATE,
|
|
||||||
.buffer_size = UART_BUFFER_SIZE,
|
|
||||||
.init = uart16550_init,
|
|
||||||
.open = uart16550_open,
|
|
||||||
.close = uart16550_close,
|
|
||||||
.read = uart16550_read,
|
|
||||||
.write = uart16550_write,
|
|
||||||
.tx_is_busy = uart16550_tx_is_busy,
|
|
||||||
.rx_data_is_avail = uart16550_rx_data_is_avail,
|
|
||||||
.get_rx_err = uart16550_get_rx_err,
|
|
||||||
|
|
||||||
|
spinlock_obtain(&uart_tx_lock);
|
||||||
|
for (i = 0U; i < len; i++) {
|
||||||
|
/* Transmit character */
|
||||||
|
uart16550_putc(buf);
|
||||||
|
if (*buf == '\n') {
|
||||||
|
/* Append '\r', no need change the len */
|
||||||
|
uart16550_putc("\r");
|
||||||
|
}
|
||||||
|
buf++;
|
||||||
}
|
}
|
||||||
};
|
spinlock_release(&uart_tx_lock);
|
||||||
|
return (int)len;
|
||||||
|
}
|
||||||
|
|
||||||
void uart16550_set_property(int enabled, int port_mapped, uint64_t base_addr)
|
void uart16550_set_property(int enabled, int port_mapped, uint64_t base_addr)
|
||||||
{
|
{
|
||||||
uart_enabled = enabled;
|
uart_enabled = enabled;
|
||||||
serial_port_mapped = port_mapped;
|
serial_port_mapped = port_mapped;
|
||||||
Tgt_Uarts[0].base_address = base_addr;
|
uart_base_address = base_addr;
|
||||||
}
|
}
|
||||||
|
@ -8,34 +8,30 @@
|
|||||||
#define UART16550_H
|
#define UART16550_H
|
||||||
|
|
||||||
/* Register / bit definitions for 16c550 uart */
|
/* Register / bit definitions for 16c550 uart */
|
||||||
#define UART16550_RBR 0x00U
|
|
||||||
/*receive buffer register | base+00h, dlab=0b r*/
|
/*receive buffer register | base+00h, dlab=0b r*/
|
||||||
#define UART16550_THR 0x00U
|
#define UART16550_RBR 0x00U
|
||||||
/*transmit holding register | base+00h, dlab=0b w*/
|
/*transmit holding register | base+00h, dlab=0b w*/
|
||||||
#define UART16550_DLL 0x00U
|
#define UART16550_THR 0x00U
|
||||||
/*divisor least significant byte | base+00h, dlab=1b rw*/
|
/*divisor least significant byte | base+00h, dlab=1b rw*/
|
||||||
#define UART16550_IER 0x01U
|
#define UART16550_DLL 0x00U
|
||||||
/*interrupt enable register | base+01h, dlab=0b rw*/
|
/*interrupt enable register | base+01h, dlab=0b rw*/
|
||||||
#define UART16550_DLM 0x01U
|
#define UART16550_IER 0x01U
|
||||||
/*divisor most significant byte | base+01h, dlab=1b rw*/
|
/*divisor most significant byte | base+01h, dlab=1b rw*/
|
||||||
#define UART16550_IIR 0x02U
|
#define UART16550_DLM 0x01U
|
||||||
/*interrupt identification register | base+02h, dlab=0b r*/
|
/*interrupt identification register | base+02h, dlab=0b r*/
|
||||||
#define UART16550_FCR 0x02U
|
#define UART16550_IIR 0x02U
|
||||||
/*fifo control register | base+02h, dlab=0b w*/
|
/*fifo control register | base+02h, dlab=0b w*/
|
||||||
#define UART16550_LCR 0x03U
|
#define UART16550_FCR 0x02U
|
||||||
/*line control register | base+03h, dlab=xb rw*/
|
/*line control register | base+03h, dlab=xb rw*/
|
||||||
#define UART16550_MCR 0x04U
|
#define UART16550_LCR 0x03U
|
||||||
/*modem control register, only uart0 | base+04h, dlab=xb rw*/
|
/*modem control register, only uart0 | base+04h, dlab=xb rw*/
|
||||||
#define UART16550_LSR 0x05U
|
#define UART16550_MCR 0x04U
|
||||||
/*line status register | base+05h, dlab=xb r*/
|
/*line status register | base+05h, dlab=xb r*/
|
||||||
#define UART16550_MSR 0x06U
|
#define UART16550_LSR 0x05U
|
||||||
/*modem status register, only uart0 | base+06h, dlab=xb r*/
|
/*modem status register, only uart0 | base+06h, dlab=xb r*/
|
||||||
#define UART16550_SCR 0x07U
|
#define UART16550_MSR 0x06U
|
||||||
/*scratch pad register | base+07h, dlab=xb rw*/
|
/*scratch pad register | base+07h, dlab=xb rw*/
|
||||||
#define UART16550_MDR1 0x08U
|
#define UART16550_SCR 0x07U
|
||||||
#define UARTML7213_BRCSR 0x0eU
|
|
||||||
/*baud rate reference clock select register dlab xb*/
|
|
||||||
#define UARTML7213_SRST 0x0fU /*Soft Reset Register dlab xb*/
|
|
||||||
|
|
||||||
/* value definitions for IIR */
|
/* value definitions for IIR */
|
||||||
#define IIR_FIFO_MASK 0xc0U /* set if FIFOs are enabled */
|
#define IIR_FIFO_MASK 0xc0U /* set if FIFOs are enabled */
|
||||||
@ -103,4 +99,17 @@
|
|||||||
|
|
||||||
#define UART_IER_DISABLE_ALL 0x00000000U
|
#define UART_IER_DISABLE_ALL 0x00000000U
|
||||||
|
|
||||||
|
#define BAUD_9600 9600
|
||||||
|
#define BAUD_115200 115200
|
||||||
|
#define BAUD_460800 460800
|
||||||
|
|
||||||
|
/* CPU oscillator clock */
|
||||||
|
#define CPU_OSC_CLOCK 1843200 /* 1.8432 MHz */
|
||||||
|
/* UART hardware definitions */
|
||||||
|
#define UART_CLOCK_RATE CPU_OSC_CLOCK
|
||||||
|
|
||||||
|
void uart16550_init(void);
|
||||||
|
char uart16550_getc(void);
|
||||||
|
int uart16550_puts(const char *buf, uint32_t len);
|
||||||
|
|
||||||
#endif /* !UART16550_H */
|
#endif /* !UART16550_H */
|
||||||
|
@ -31,14 +31,11 @@
|
|||||||
#include <hypervisor.h>
|
#include <hypervisor.h>
|
||||||
|
|
||||||
#include "uart16550.h"
|
#include "uart16550.h"
|
||||||
#include "serial_internal.h"
|
|
||||||
|
|
||||||
#define COM1_BASE 0x3F8
|
#define COM1_BASE 0x3F8
|
||||||
#define COM1_IRQ 4
|
#define COM1_IRQ 4
|
||||||
#define DEFAULT_RCLK 1843200
|
#define RX_FIFO_SIZE 256
|
||||||
#define DEFAULT_BAUD 9600
|
#define TX_FIFO_SIZE 65536
|
||||||
#define RX_SIZE 256
|
|
||||||
#define TX_SIZE 65536
|
|
||||||
|
|
||||||
#define vuart_lock_init(vu) spinlock_init(&((vu)->lock))
|
#define vuart_lock_init(vu) spinlock_init(&((vu)->lock))
|
||||||
#define vuart_lock(vu) spinlock_obtain(&((vu)->lock))
|
#define vuart_lock(vu) spinlock_obtain(&((vu)->lock))
|
||||||
@ -99,7 +96,7 @@ static int fifo_numchars(struct fifo *fifo)
|
|||||||
*
|
*
|
||||||
* Return an interrupt reason if one is available.
|
* Return an interrupt reason if one is available.
|
||||||
*/
|
*/
|
||||||
static uint8_t uart_intr_reason(struct vuart *vu)
|
static uint8_t vuart_intr_reason(struct vuart *vu)
|
||||||
{
|
{
|
||||||
if ((vu->lsr & LSR_OE) != 0 && (vu->ier & IER_ELSI) != 0) {
|
if ((vu->lsr & LSR_OE) != 0 && (vu->ier & IER_ELSI) != 0) {
|
||||||
return IIR_RLS;
|
return IIR_RLS;
|
||||||
@ -112,30 +109,15 @@ static uint8_t uart_intr_reason(struct vuart *vu)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void uart_init(struct vuart *vu)
|
|
||||||
{
|
|
||||||
uint16_t divisor;
|
|
||||||
|
|
||||||
divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
|
|
||||||
vu->dll = divisor;
|
|
||||||
vu->dlh = divisor >> 16;
|
|
||||||
|
|
||||||
vu->active = false;
|
|
||||||
vu->base = COM1_BASE;
|
|
||||||
fifo_init(&vu->rxfifo, RX_SIZE);
|
|
||||||
fifo_init(&vu->txfifo, TX_SIZE);
|
|
||||||
vuart_lock_init(vu);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Toggle the COM port's intr pin depending on whether or not we have an
|
* Toggle the COM port's intr pin depending on whether or not we have an
|
||||||
* interrupt condition to report to the processor.
|
* interrupt condition to report to the processor.
|
||||||
*/
|
*/
|
||||||
static void uart_toggle_intr(struct vuart *vu)
|
static void vuart_toggle_intr(struct vuart *vu)
|
||||||
{
|
{
|
||||||
uint8_t intr_reason;
|
uint8_t intr_reason;
|
||||||
|
|
||||||
intr_reason = uart_intr_reason(vu);
|
intr_reason = vuart_intr_reason(vu);
|
||||||
|
|
||||||
if (intr_reason != IIR_NOPEND) {
|
if (intr_reason != IIR_NOPEND) {
|
||||||
if (vu->vm->vpic != NULL) {
|
if (vu->vm->vpic != NULL) {
|
||||||
@ -151,7 +133,7 @@ static void uart_toggle_intr(struct vuart *vu)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void uart_write(__unused struct vm_io_handler *hdlr,
|
static void vuart_write(__unused struct vm_io_handler *hdlr,
|
||||||
struct vm *vm, uint16_t offset_arg,
|
struct vm *vm, uint16_t offset_arg,
|
||||||
__unused size_t width, uint32_t value)
|
__unused size_t width, uint32_t value)
|
||||||
{
|
{
|
||||||
@ -227,11 +209,11 @@ static void uart_write(__unused struct vm_io_handler *hdlr,
|
|||||||
}
|
}
|
||||||
|
|
||||||
done:
|
done:
|
||||||
uart_toggle_intr(vu);
|
vuart_toggle_intr(vu);
|
||||||
vuart_unlock(vu);
|
vuart_unlock(vu);
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t uart_read(__unused struct vm_io_handler *hdlr,
|
static uint32_t vuart_read(__unused struct vm_io_handler *hdlr,
|
||||||
struct vm *vm, uint16_t offset_arg,
|
struct vm *vm, uint16_t offset_arg,
|
||||||
__unused size_t width)
|
__unused size_t width)
|
||||||
{
|
{
|
||||||
@ -265,7 +247,7 @@ static uint32_t uart_read(__unused struct vm_io_handler *hdlr,
|
|||||||
break;
|
break;
|
||||||
case UART16550_IIR:
|
case UART16550_IIR:
|
||||||
iir = ((vu->fcr & FCR_FIFOE) != 0) ? IIR_FIFO_MASK : 0;
|
iir = ((vu->fcr & FCR_FIFOE) != 0) ? IIR_FIFO_MASK : 0;
|
||||||
intr_reason = uart_intr_reason(vu);
|
intr_reason = vuart_intr_reason(vu);
|
||||||
/*
|
/*
|
||||||
* Deal with side effects of reading the IIR register
|
* Deal with side effects of reading the IIR register
|
||||||
*/
|
*/
|
||||||
@ -306,7 +288,7 @@ static uint32_t uart_read(__unused struct vm_io_handler *hdlr,
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
done:
|
done:
|
||||||
uart_toggle_intr(vu);
|
vuart_toggle_intr(vu);
|
||||||
vuart_unlock(vu);
|
vuart_unlock(vu);
|
||||||
return reg;
|
return reg;
|
||||||
}
|
}
|
||||||
@ -315,22 +297,18 @@ static void vuart_register_io_handler(struct vm *vm)
|
|||||||
{
|
{
|
||||||
struct vm_io_range range = {
|
struct vm_io_range range = {
|
||||||
.flags = IO_ATTR_RW,
|
.flags = IO_ATTR_RW,
|
||||||
.base = 0x3f8,
|
.base = COM1_BASE,
|
||||||
.len = 8U
|
.len = 8U
|
||||||
};
|
};
|
||||||
|
|
||||||
register_io_emulation_handler(vm, &range, uart_read, uart_write);
|
register_io_emulation_handler(vm, &range, vuart_read, vuart_write);
|
||||||
}
|
}
|
||||||
|
|
||||||
void vuart_console_tx_chars(void)
|
/**
|
||||||
|
* @pre vu != NULL
|
||||||
|
*/
|
||||||
|
void vuart_console_tx_chars(struct vuart *vu)
|
||||||
{
|
{
|
||||||
struct vuart *vu;
|
|
||||||
|
|
||||||
vu = vuart_console_active();
|
|
||||||
if (vu == NULL) {
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
vuart_lock(vu);
|
vuart_lock(vu);
|
||||||
while (fifo_numchars(&vu->txfifo) > 0) {
|
while (fifo_numchars(&vu->txfifo) > 0) {
|
||||||
printf("%c", fifo_getchar(&vu->txfifo));
|
printf("%c", fifo_getchar(&vu->txfifo));
|
||||||
@ -338,46 +316,27 @@ void vuart_console_tx_chars(void)
|
|||||||
vuart_unlock(vu);
|
vuart_unlock(vu);
|
||||||
}
|
}
|
||||||
|
|
||||||
void vuart_console_rx_chars(uint32_t serial_handle)
|
/**
|
||||||
|
* @pre vu != NULL
|
||||||
|
* @pre vu->active == true
|
||||||
|
*/
|
||||||
|
void vuart_console_rx_chars(struct vuart *vu)
|
||||||
{
|
{
|
||||||
struct vuart *vu;
|
char ch = -1;
|
||||||
uint32_t vbuf_len;
|
|
||||||
char buffer[100];
|
|
||||||
uint32_t buf_idx = 0;
|
|
||||||
|
|
||||||
if (serial_handle == SERIAL_INVALID_HANDLE) {
|
|
||||||
pr_err("%s: invalid serial handle 0x%llx\n",
|
|
||||||
__func__, serial_handle);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
vu = vuart_console_active();
|
|
||||||
if (vu == NULL) {
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
vuart_lock(vu);
|
vuart_lock(vu);
|
||||||
/* Get data from serial */
|
/* Get data from physical uart */
|
||||||
vbuf_len = serial_gets(serial_handle, buffer, 100);
|
ch = uart16550_getc();
|
||||||
if (vbuf_len != 0U) {
|
|
||||||
while (buf_idx < vbuf_len) {
|
|
||||||
if (buffer[buf_idx] == GUEST_CONSOLE_TO_HV_SWITCH_KEY) {
|
|
||||||
/* Switch the console */
|
|
||||||
shell_switch_console();
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
buf_idx++;
|
|
||||||
}
|
|
||||||
if (vu->active != false) {
|
|
||||||
buf_idx = 0;
|
|
||||||
while (buf_idx < vbuf_len) {
|
|
||||||
fifo_putchar(&vu->rxfifo, buffer[buf_idx]);
|
|
||||||
buf_idx++;
|
|
||||||
}
|
|
||||||
|
|
||||||
uart_toggle_intr(vu);
|
if (ch == GUEST_CONSOLE_TO_HV_SWITCH_KEY) {
|
||||||
}
|
/* Switch the console */
|
||||||
|
shell_switch_console();
|
||||||
}
|
}
|
||||||
|
if (ch != -1) {
|
||||||
|
fifo_putchar(&vu->rxfifo, ch);
|
||||||
|
vuart_toggle_intr(vu);
|
||||||
|
}
|
||||||
|
|
||||||
vuart_unlock(vu);
|
vuart_unlock(vu);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -398,11 +357,22 @@ struct vuart *vuart_console_active(void)
|
|||||||
void *vuart_init(struct vm *vm)
|
void *vuart_init(struct vm *vm)
|
||||||
{
|
{
|
||||||
struct vuart *vu;
|
struct vuart *vu;
|
||||||
|
uint16_t divisor;
|
||||||
|
|
||||||
vu = calloc(1, sizeof(struct vuart));
|
vu = calloc(1, sizeof(struct vuart));
|
||||||
ASSERT(vu != NULL, "");
|
ASSERT(vu != NULL, "");
|
||||||
uart_init(vu);
|
|
||||||
|
/* Set baud rate*/
|
||||||
|
divisor = UART_CLOCK_RATE / BAUD_9600 / 16;
|
||||||
|
vu->dll = divisor;
|
||||||
|
vu->dlh = divisor >> 16;
|
||||||
|
|
||||||
|
vu->active = false;
|
||||||
|
vu->base = COM1_BASE;
|
||||||
vu->vm = vm;
|
vu->vm = vm;
|
||||||
|
fifo_init(&vu->rxfifo, RX_FIFO_SIZE);
|
||||||
|
fifo_init(&vu->txfifo, TX_FIFO_SIZE);
|
||||||
|
vuart_lock_init(vu);
|
||||||
vuart_register_io_handler(vm);
|
vuart_register_io_handler(vm);
|
||||||
|
|
||||||
return vu;
|
return vu;
|
||||||
|
@ -16,16 +16,6 @@ extern struct hv_timer console_timer;
|
|||||||
|
|
||||||
void console_init(void);
|
void console_init(void);
|
||||||
|
|
||||||
/** Writes a NUL terminated string to the console.
|
|
||||||
*
|
|
||||||
* @param str A pointer to the NUL terminated string to write.
|
|
||||||
*
|
|
||||||
* @return The number of characters written or -1 if an error occurred
|
|
||||||
* and no character was written.
|
|
||||||
*/
|
|
||||||
|
|
||||||
int console_puts(const char *s_arg);
|
|
||||||
|
|
||||||
/** Writes a given number of characters to the console.
|
/** Writes a given number of characters to the console.
|
||||||
*
|
*
|
||||||
* @param str A pointer to character array to write.
|
* @param str A pointer to character array to write.
|
||||||
@ -45,7 +35,9 @@ int console_write(const char *s_arg, size_t len);
|
|||||||
* occurred before any character was written.
|
* occurred before any character was written.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
int console_putc(int ch);
|
void console_putc(const char *ch);
|
||||||
|
char console_getc(void);
|
||||||
|
int console_gets(char *buffer, uint32_t length);
|
||||||
|
|
||||||
void console_setup_timer(void);
|
void console_setup_timer(void);
|
||||||
|
|
||||||
@ -65,20 +57,16 @@ static inline void resume_console(void)
|
|||||||
static inline void console_init(void)
|
static inline void console_init(void)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
static inline int console_puts(__unused const char *str)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
static inline int console_write(__unused const char *str,
|
static inline int console_write(__unused const char *str,
|
||||||
__unused size_t len)
|
__unused size_t len)
|
||||||
{
|
{
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
static inline int console_putc(__unused int ch)
|
static inline void console_putc(__unused const char *ch) { }
|
||||||
{
|
static inline int console_getc(void) { return 0; }
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
static inline int console_gets(char *buffer, uint32_t length) { return 0; }
|
||||||
static inline void console_setup_timer(void) {}
|
static inline void console_setup_timer(void) {}
|
||||||
static inline uint32_t get_serial_handle(void) { return 0; }
|
static inline uint32_t get_serial_handle(void) { return 0; }
|
||||||
|
|
||||||
|
@ -63,8 +63,8 @@ struct vuart {
|
|||||||
#ifdef HV_DEBUG
|
#ifdef HV_DEBUG
|
||||||
void *vuart_init(struct vm *vm);
|
void *vuart_init(struct vm *vm);
|
||||||
struct vuart *vuart_console_active(void);
|
struct vuart *vuart_console_active(void);
|
||||||
void vuart_console_tx_chars(void);
|
void vuart_console_tx_chars(struct vuart *vu);
|
||||||
void vuart_console_rx_chars(uint32_t serial_handle);
|
void vuart_console_rx_chars(struct vuart *vu);
|
||||||
#else
|
#else
|
||||||
static inline void *vuart_init(__unused struct vm *vm)
|
static inline void *vuart_init(__unused struct vm *vm)
|
||||||
{
|
{
|
||||||
@ -74,11 +74,8 @@ static inline struct vuart *vuart_console_active(void)
|
|||||||
{
|
{
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
static inline void vuart_console_tx_chars(void) {}
|
static inline void vuart_console_tx_chars(__unused struct vuart *vu) {}
|
||||||
static inline void vuart_console_rx_chars(
|
static inline void vuart_console_rx_chars(__unused struct vuart *vu) {}
|
||||||
__unused uint32_t serial_handle)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
#endif /*HV_DEBUG*/
|
#endif /*HV_DEBUG*/
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
@ -8,7 +8,6 @@
|
|||||||
#define HV_DEBUG_H
|
#define HV_DEBUG_H
|
||||||
|
|
||||||
#include <logmsg.h>
|
#include <logmsg.h>
|
||||||
#include <serial.h>
|
|
||||||
#include <vuart.h>
|
#include <vuart.h>
|
||||||
#include <console.h>
|
#include <console.h>
|
||||||
#include <dump.h>
|
#include <dump.h>
|
||||||
|
Loading…
Reference in New Issue
Block a user