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HV: extract functions from code to improve code reuse and readability
Create 2 functions from code: pci_base_from_size_mask vdev_pt_remap_mem_vbar Use vbar in place of vdev->bar[idx] by setting vbar to &vdev->bar[idx] Change base to uint64_t to accommodate 64-bit MMIO bar size masking in subsequent commits Tracked-On: #3241 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Reviewed-by: Eddie Dong <eddie.dong@intel.com>
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@ -305,6 +305,22 @@ static void vdev_pt_remap_generic_mem_vbar(struct pci_vdev *vdev, uint32_t idx)
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}
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}
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/**
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* @pre vdev != NULL
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*/
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static void vdev_pt_remap_mem_vbar(struct pci_vdev *vdev, uint32_t idx)
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{
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bool is_msix_table_bar;
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is_msix_table_bar = (has_msix_cap(vdev) && (idx == vdev->msix.table_bar));
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if (is_msix_table_bar) {
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vdev_pt_remap_msix_table_bar(vdev);
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} else {
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vdev_pt_remap_generic_mem_vbar(vdev, idx);
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}
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}
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/**
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* @brief Set the base address portion of the vbar base address register (32-bit)
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* base: bar value with flags portion masked off
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@ -335,30 +351,26 @@ static void set_vbar_base(struct pci_bar *vbar, uint32_t base)
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static void vdev_pt_write_vbar(struct pci_vdev *vdev, uint32_t offset, uint32_t val)
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{
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uint32_t idx;
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uint32_t base, mask;
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uint64_t base;
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bool bar_update_normal;
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bool is_msix_table_bar;
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struct pci_bar *vbar;
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base = 0U;
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base = 0UL;
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idx = (offset - pci_bar_offset(0U)) >> 2U;
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mask = ~(vdev->bar[idx].size - 1U);
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bar_update_normal = (val != (uint32_t)~0U);
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vbar = &vdev->bar[idx];
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switch (vdev->bar[idx].type) {
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case PCIBAR_NONE:
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break;
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case PCIBAR_MEM32:
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bar_update_normal = (val != (uint32_t)~0U);
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is_msix_table_bar = (has_msix_cap(vdev) && (idx == vdev->msix.table_bar));
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base = val & mask;
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set_vbar_base(&vdev->bar[idx], base);
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base = pci_base_from_size_mask(vbar->size, (uint64_t)val);
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set_vbar_base(vbar, (uint32_t)base);
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if (bar_update_normal) {
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if (is_msix_table_bar) {
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vdev_pt_remap_msix_table_bar(vdev);
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} else {
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vdev_pt_remap_generic_mem_vbar(vdev, idx);
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}
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vdev_pt_remap_mem_vbar(vdev, idx);
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}
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break;
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@ -368,7 +380,7 @@ static void vdev_pt_write_vbar(struct pci_vdev *vdev, uint32_t offset, uint32_t
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}
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/* Write the vbar value to corresponding virtualized vbar reg */
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pci_vdev_write_cfg_u32(vdev, offset, vdev->bar[idx].reg.value);
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pci_vdev_write_cfg_u32(vdev, offset, vbar->reg.value);
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}
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/**
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@ -266,6 +266,19 @@ static inline enum pci_bar_type pci_get_bar_type(uint32_t val)
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return type;
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}
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/**
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* Given bar size and raw bar value, return bar base address by masking off its lower flag bits
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* size/val: all in 64-bit values to accommodate 64-bit MMIO bar size masking
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*/
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static inline uint64_t pci_base_from_size_mask(uint64_t size, uint64_t val)
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{
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uint64_t mask;
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mask = ~(size - 1UL);
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return (mask & val);
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}
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static inline uint8_t pci_bus(uint16_t bdf)
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{
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return (uint8_t)((bdf >> 8U) & 0xFFU);
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