[FIXME] hv: smpcall: riscv: add placeholder implementations for dependent code

This patch provides dummy implementations of functions and data
structures required for the IPI and SMP call on RISC-V.
It serves as a placeholder to ensure RISC-V builds pass and
is not needed for the final merge.

Official implementations are still WIP by other engineers:

 - To be provided in the library patchset (by Haoyu):
    uint16_t ffs64(uint64_t value);
    bool bitmap_test(uint16_t nr, const volatile uint64_t *addr);
    void bitmap_clear_lock(uint16_t nr_arg, volatile uint64_t *addr);
    void bitmap_clear_nolock(uint16_t nr_arg, volatile uint64_t *addr);
    uint64_t atomic_cmpxchg64(volatile uint64_t *ptr, uint64_t old, uint64_t new);

 - To be provided in the platform initialization patchset (by Hang):
    void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync);
    bool is_pcpu_active(uint16_t pcpu_id);
    uint16_t get_pcpu_id(void);

----------
Changelog:
 * Split per_cpu.h implementation into a separate commit.

Tracked-On: #8786
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>

hypervisor/include/arch/riscv/asm/cpu.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2025 Intel Corporation.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef RISCV_CPU_H
+#define RISCV_CPU_H
+
+#include <types.h>
+
+static inline void wait_sync_change(__unused volatile const uint64_t *sync, __unused uint64_t wake_sync)
+{
+	/**
+	 * Dummy implementation.
+	 * Official implementations are to be provided in the platform initialization patchset (by Hang).
+	 */
+}
+
+static inline bool is_pcpu_active(__unused uint16_t pcpu_id)
+{
+	/**
+	 * Dummy implementation.
+	 * Official implementations are to be provided in the platform initialization patchset (by Hang).
+	 */
+	return true;
+}
+
+static inline uint16_t get_pcpu_id(void)
+{
+	/**
+	 * Dummy implementation.
+	 * Official implementations are to be provided in the platform initialization patchset (by Hang).
+	 */
+	return 0U;
+}
+
+#endif /* RISCV_CPU_H */

hypervisor/include/arch/riscv/asm/lib/atomic.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2025 Intel Corporation.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef RISCV_ATOMIC_H
+#define RISCV_ATOMIC_H
+
+#include <types.h>
+
+static inline uint64_t atomic_cmpxchg64(__unused volatile uint64_t *ptr, __unused uint64_t old, __unused uint64_t new)
+{
+	/**
+	 * Dummy implementation.
+	 * Official implementations are to be provided in the library patchset (by Haoyu).
+	 */
+	return 0UL;
+}
+
+#endif /* RISCV_ATOMIC_H */

hypervisor/include/arch/riscv/asm/lib/bits.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2025 Intel Corporation.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef RISCV_BITS_H
+#define RISCV_BITS_H
+
+#include <types.h>
+
+uint16_t ffs64(__unused uint64_t value)
+{
+	/**
+	 * Dummy implementation.
+	 * Official implementations are to be provided in the library patchset (by Haoyu).
+	 */
+	return 0U;
+}
+
+bool bitmap_test(__unused uint16_t nr, __unused const volatile uint64_t *addr)
+{
+	/**
+	 * Dummy implementation.
+	 * Official implementations are to be provided in the library patchset (by Haoyu).
+	 */
+	return true;
+}
+
+void bitmap_clear_lock(__unused uint16_t nr_arg, __unused volatile uint64_t *addr)
+{
+	/**
+	 * Dummy implementation.
+	 * Official implementations are to be provided in the library patchset (by Haoyu).
+	 */
+}
+
+void bitmap_clear_nolock(__unused uint16_t nr_arg, __unused volatile uint64_t *addr)
+{
+	/**
+	 * Dummy implementation.
+	 * Official implementations are to be provided in the library patchset (by Haoyu).
+	 */
+}
+
+#endif /* RISCV_BITS_H */