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https://github.com/projectacrn/acrn-hypervisor.git
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hv: add more MSR definitions
- add definitions of all architectural MSRs - add definitions of majority of non architectural MSRs The non-architectural MSR definitions are specific to particular CPU model or family. e.g. MSR 0xE01 could refer to different MSRs in difference processors, and in this patch, MSR_R0_PMON_BOX_STATUS is chosen without any particular reasons. MSR_R0_PMON_BOX_STATUS in Xeon Processor 7500 Series MSR_C0_PMON_EVNTSEL0 in Xeon E5 V3 family MSR_UNC_PERF_GLOBAL_CTRL in 6th plus generations Core Processors Tracked-On: #1867 Signed-off-by: Zide Chen <zide.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Zide Chen
wenlingz
parent
6372548e11
commit
b22c8b696b
@ -47,7 +47,7 @@
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#define MSR_IA32_MTRR_CAP 0x000000FEU
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#define MSR_IA32_ARCH_CAPABILITIES 0x0000010AU
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#define MSR_IA32_FLUSH_CMD 0x0000010BU
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#define MISC_FEATURE_ENABLES 0x00000140U
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#define MSR_MISC_FEATURE_ENABLES 0x00000140U
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#define MSR_IA32_SYSENTER_CS 0x00000174U
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#define MSR_IA32_SYSENTER_ESP 0x00000175U
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#define MSR_IA32_SYSENTER_EIP 0x00000176U
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@ -65,6 +65,8 @@
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#define MSR_IA32_THERM_STATUS 0x0000019CU
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#define MSR_IA32_MISC_ENABLE 0x000001A0U
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#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0U
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#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1U
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#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2U
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#define MSR_IA32_DEBUGCTL 0x000001D9U
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#define MSR_IA32_SMRR_PHYSBASE 0x000001F2U
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#define MSR_IA32_SMRR_PHYSMASK 0x000001F3U
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@ -125,6 +127,7 @@
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#define MSR_IA32_MC19_CTL2 0x00000293U
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#define MSR_IA32_MC20_CTL2 0x00000294U
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#define MSR_IA32_MC21_CTL2 0x00000295U
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#define MSR_IA32_MC31_CTL2 0x0000029FU
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#define MSR_IA32_MTRR_DEF_TYPE 0x000002FFU
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#define MSR_SGXOWNEREPOCH0 0x00000300U
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#define MSR_SGXOWNEREPOCH1 0x00000301U
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@ -227,6 +230,10 @@
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#define MSR_IA32_MC21_STATUS 0x00000455U
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#define MSR_IA32_MC21_ADDR 0x00000456U
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#define MSR_IA32_MC21_MISC 0x00000457U
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#define MSR_IA32_MC28_CTL 0x00000470U
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#define MSR_IA32_MC28_STATUS 0x00000471U
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#define MSR_IA32_MC28_ADDR 0x00000472U
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#define MSR_IA32_MC28_MISC 0x00000473U
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#define MSR_IA32_VMX_BASIC 0x00000480U
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#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481U
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#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482U
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@ -329,44 +336,180 @@
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#define MSR_IA32_QM_CTR 0x00000C8EU
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#define MSR_IA32_PQR_ASSOC 0x00000C8FU
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#define MSR_IA32_L3_MASK_0 0x00000C90U
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#define MSR_IA32_XSS 0x00000DA0U
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#define MSR_IA32_PKG_HDC_CTL 0x00000DB0U
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#define MSR_IA32_PM_CTL1 0x00000DB1U
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#define MSR_IA32_THREAD_STALL 0x00000DB2U
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#define MSR_IA32_L2_MASK_0 0x00000D10U
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#define MSR_IA32_BNDCFGS 0x00000D90U
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#define MSR_IA32_EFER 0xC0000080U
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#define MSR_IA32_STAR 0xC0000081U
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#define MSR_IA32_LSTAR 0xC0000082U
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#define MSR_IA32_CSTAR 0xC0000083U
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#define MSR_IA32_FMASK 0xC0000084U
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#define MSR_IA32_FS_BASE 0xC0000100U
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#define MSR_IA32_GS_BASE 0xC0000101U
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#define MSR_IA32_KERNEL_GS_BASE 0xC0000102U
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#define MSR_IA32_TSC_AUX 0xC0000103U
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/* ATOM specific MSRs */
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#define MSR_ATOM_EBL_CR_POWERON 0x0000002AU
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#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040U
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#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041U
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#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042U
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#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043U
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#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044U
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#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045U
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#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046U
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#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047U
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#define MSR_ATOM_LASTBRANCH_0_TO_LIP 0x00000060U
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#define MSR_ATOM_LASTBRANCH_1_TO_LIP 0x00000061U
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#define MSR_ATOM_LASTBRANCH_2_TO_LIP 0x00000062U
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#define MSR_ATOM_LASTBRANCH_3_TO_LIP 0x00000063U
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#define MSR_ATOM_LASTBRANCH_4_TO_LIP 0x00000064U
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#define MSR_ATOM_LASTBRANCH_5_TO_LIP 0x00000065U
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#define MSR_ATOM_LASTBRANCH_6_TO_LIP 0x00000066U
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#define MSR_ATOM_LASTBRANCH_7_TO_LIP 0x00000067U
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/* Scalable bus speed */
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#define MSR_ATOM_FSB_FREQ 0x000000CDU
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/* non-architectural MSRs */
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#define MSR_EBL_CR_POWERON 0x0000002AU
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#define MSR_EBC_SOFT_POWERON 0x0000002BU
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#define MSR_EBC_FREQUENCY_ID 0x0000002CU
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#define MSR_SMI_COUNT 0x00000034U
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#define MSR_CORE_THREAD_COUNT 0x00000035U
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#define MSR_LASTBRANCH_0_FROM_IP 0x00000040U
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#define MSR_LASTBRANCH_1_FROM_IP 0x00000041U
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#define MSR_LASTBRANCH_2_FROM_IP 0x00000042U
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#define MSR_LASTBRANCH_3_FROM_IP 0x00000043U
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#define MSR_LASTBRANCH_4_FROM_IP 0x00000044U
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#define MSR_LASTBRANCH_5_FROM_IP 0x00000045U
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#define MSR_LASTBRANCH_6_FROM_IP 0x00000046U
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#define MSR_LASTBRANCH_7_FROM_IP 0x00000047U
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#define MSR_PPIN_CTL 0x0000004EU
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#define MSR_PPIN 0x0000004FU
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#define MSR_THREAD_ID_INFO 0x00000053U
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#define MSR_LASTBRANCH_0_TO_LIP 0x00000060U
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#define MSR_LASTBRANCH_1_TO_LIP 0x00000061U
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#define MSR_LASTBRANCH_2_TO_LIP 0x00000062U
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#define MSR_LASTBRANCH_3_TO_LIP 0x00000063U
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#define MSR_LASTBRANCH_4_TO_LIP 0x00000064U
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#define MSR_LASTBRANCH_5_TO_LIP 0x00000065U
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#define MSR_LASTBRANCH_6_TO_LIP 0x00000066U
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#define MSR_LASTBRANCH_7_TO_LIP 0x00000067U
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#define MSR_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080U
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#define MSR_FSB_FREQ 0x000000CDU
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#define MSR_PLATFORM_INFO 0x000000CEU
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/* L2 hardware enabled */
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#define MSR_ATOM_BBL_CR_CTL3 0x0000011EU
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#define MSR_ATOM_THERM2_CTL 0x0000019DU
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#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9U
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#define MSR_ATOM_LER_FROM_LIP 0x000001DDU
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#define MSR_ATOM_LER_TO_LIP 0x000001DEU
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#define MSR_PKG_CST_CONFIG_CONTROL 0x000000E2U
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#define MSR_PMG_IO_CAPTURE_BASE 0x000000E4U
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#define MSR_UNDOCUMENTED_TJMAX 0x000000EEU
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#define MSR_BBL_CR_CTL 0x00000119U
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#define MSR_BBL_CR_CTL3 0x0000011EU
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#define MSR_FEATURE_CONFIG 0x0000013CU
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#define MSR_SMM_MCA_CAP 0x0000017DU
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#define MSR_ERROR_CONTROL 0x0000017FU
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#define MSR_THERM2_CTL 0x0000019DU
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#define MSR_PLATFORM_BRV 0x000001A1U
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#define MSR_TEMPERATURE_TARGET 0x000001A2U
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#define MSR_MISC_FEATURE_CONTROL 0x000001A4U
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#define MSR_OFFCORE_RSP_0 0x000001A6U
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#define MSR_OFFCORE_RSP_1 0x000001A7U
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#define MSR_MISC_PWR_MGMT 0x000001AAU
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#define MSR_TURBO_POWER_CURRENT_LIMIT 0x000001ACU
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#define MSR_TURBO_RATIO_LIMIT 0x000001ADU
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#define MSR_TURBO_GROUP_CORECNT 0x000001AEU
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#define MSR_TURBO_RATIO_LIMIT2 0x000001AFU
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#define MSR_LBR_SELECT 0x000001C8U
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#define MSR_LASTBRANCH_TOS 0x000001DAU
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#define MSR_LASTBRANCH_0 0x000001DBU
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#define MSR_LASTBRANCH_1 0x000001DCU
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#define MSR_LASTBRANCH_2 0x000001DDU
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#define MSR_LASTBRANCH_3 0x000001DEU
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#define MSR_PRMRR_VALID_CONFIG 0x000001FBU
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#define MSR_POWER_CTL 0x000001FCU
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#define MSR_BR_DETECT_CTRL 0x00000350U
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#define MSR_BR_DETECT_STATUS 0x00000351U
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#define MSR_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393U
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#define MSR_UNCORE_FIXED_CTR0 0x00000394U
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#define MSR_UNCORE_FIXED_CTR_CTRL 0x00000395U
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#define MSR_UNCORE_ADDR_OPCODE_MATCH 0x00000396U
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#define MSR_UNCORE_PMC0 0x000003B0U
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#define MSR_UNCORE_PMC1 0x000003B1U
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#define MSR_UNCORE_PMC2 0x000003B2U
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#define MSR_UNCORE_PMC3 0x000003B3U
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#define MSR_UNCORE_PMC4 0x000003B4U
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#define MSR_UNCORE_PMC5 0x000003B5U
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#define MSR_UNCORE_PMC6 0x000003B6U
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#define MSR_UNCORE_PMC7 0x000003B7U
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#define MSR_UNCORE_PERFEVTSEL0 0x000003C0U
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#define MSR_UNCORE_PERFEVTSEL1 0x000003C1U
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#define MSR_UNCORE_PERFEVTSEL2 0x000003C2U
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#define MSR_UNCORE_PERFEVTSEL3 0x000003C3U
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#define MSR_UNCORE_PERFEVTSEL4 0x000003C4U
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#define MSR_UNCORE_PERFEVTSEL5 0x000003C5U
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#define MSR_UNCORE_PERFEVTSEL6 0x000003C6U
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#define MSR_UNCORE_PERFEVTSEL7 0x000003C7U
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#define MSR_PEBS_LD_LAT 0x000003F6U
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#define MSR_PEBS_FRONTEND 0x000003F7U
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#define MSR_PKG_C2_RESIDENCY 0x000003F8U
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#define MSR_PKG_C4_RESIDENCY 0x000003F9U
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#define MSR_PKG_C6_RESIDENCY 0x000003FAU
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#define MSR_CORE_C3_RESIDENCY 0x000003FCU
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#define MSR_CORE_C6_RESIDENCY 0x000003FDU
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#define MSR_CORE_C7_RESIDENCY 0x000003FEU
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#define MSR_SMM_FEATURE_CONTROL 0x000004E0U
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#define MSR_SMM_DELAYED 0x000004E2U
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#define MSR_SMM_BLOCKED 0x000004E3U
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#define MSR_RAPL_POWER_UNIT 0x00000606U
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#define MSR_PKGC3_IRTL 0x0000060AU
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#define MSR_PKGC_IRTL1 0x0000060BU
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#define MSR_PKGC_IRTL2 0x0000060CU
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#define MSR_ATOM_PKG_C2_RESIDENCY 0x0000060DU
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#define MSR_PKG_POWER_LIMIT 0x00000610U
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#define MSR_PKG_ENERGY_STATUS 0x00000611U
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#define MSR_PKG_PERF_STATUS 0x00000613U
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#define MSR_PKG_POWER_INFO 0x00000614U
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#define MSR_DRAM_POWER_LIMIT 0x00000618U
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#define MSR_DRAM_ENERGY_STATUS 0x00000619U
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#define MSR_DRAM_PERF_STATUS 0x0000061BU
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#define MSR_DRAM_POWER_INFO 0x0000061CU
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#define MSR_PCIE_PLL_RATIO 0x0000061EU
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#define MSR_UNCORE_RATIO_LIMIT 0x00000620U
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#define MSR_PKG_C8_RESIDENCY 0x00000630U
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#define MSR_PKG_C9_RESIDENCY 0x00000631U
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#define MSR_PKG_C10_RESIDENCY 0x00000632U
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#define MSR_PKGC8_IRTL 0x00000633U
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#define MSR_PKGC9_IRTL 0x00000634U
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#define MSR_PKGC10_IRTL 0x00000635U
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#define MSR_PP0_POWER_LIMIT 0x00000638U
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#define MSR_PP0_ENERGY_STATUS 0x00000639U
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#define MSR_PP0_POLICY 0x0000063AU
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#define MSR_PP1_POWER_LIMIT 0x00000640U
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#define MSR_PP1_ENERGY_STATUS 0x00000641U
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#define MSR_PP1_POLICY 0x00000642U
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#define MSR_CONFIG_TDP_NOMINAL 0x00000648U
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#define MSR_CONFIG_TDP_LEVEL1 0x00000649U
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#define MSR_CONFIG_TDP_LEVEL2 0x0000064AU
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#define MSR_CONFIG_TDP_CONTROL 0x0000064BU
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#define MSR_TURBO_ACTIVATION_RATIO 0x0000064CU
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#define MSR_PLATFORM_ENERGY_COUNTER 0x0000064DU
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#define MSR_PPERF 0x0000064EU
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#define MSR_ATOM_CORE_PERF_LIMIT_REASONS 0X0000064FU
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#define MSR_PKG_HDC_CONFIG 0x00000652U
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#define MSR_CORE_HDC_RESIDENCY 0x00000653U
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#define MSR_PKG_HDC_SHALLOW_RESIDENCY 0x00000655U
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#define MSR_PKG_HDC_DEEP_RESIDENCY 0x00000656U
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#define MSR_WEIGHTED_CORE_C0 0x00000658U
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#define MSR_ANY_CORE_C0 0x00000659U
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#define MSR_ANY_GFXE_C0 0x0000065AU
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#define MSR_CORE_GFXE_OVERLAP_C0 0x0000065BU
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#define MSR_PLATFORM_POWER_LIMIT 0x0000065CU
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#define MSR_CORE_C1_RESIDENCY 0x00000660U
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#define MSR_MC6_RESIDENCY_COUNTER 0x00000664U
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#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668U
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#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669U
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#define MSR_ATOM_PKG_POWER_INFO 0x0000066EU
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#define MSR_RING_PERF_LIMIT_REASONS 0x00000681U
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#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690U
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#define MSR_LASTBRANCH_31_FROM_IP 0x0000069FU
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#define MSR_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0U
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#define MSR_LASTBRANCH_0_TO_IP 0x000006C0U
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#define MSR_LASTBRANCH_31_TO_IP 0x000006DFU
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#define MSR_IA32_L2_QOS_MASK_0 0x00000D10U
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#define MSR_IA32_L2_QOS_MASK_1 0x00000D11U
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#define MSR_IA32_L2_QOS_MASK_2 0x00000D12U
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#define MSR_IA32_L2_QOS_MASK_3 0x00000D13U
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#define MSR_LASTBRANCH_INFO_0 0x00000DC0U
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#define MSR_LASTBRANCH_INFO_31 0x00000DDFU
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#define MSR_R0_PMON_BOX_STATUS 0x00000E01U
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#define MSR_EMON_L3_CTR_CTL0 0x000107CCU
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#define MSR_EMON_L3_CTR_CTL1 0x000107CDU
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#define MSR_EMON_L3_CTR_CTL2 0x000107CEU
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#define MSR_EMON_L3_CTR_CTL3 0x000107CFU
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#define MSR_EMON_L3_CTR_CTL4 0x000107D0U
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#define MSR_EMON_L3_CTR_CTL5 0x000107D1U
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#define MSR_EMON_L3_CTR_CTL6 0x000107D2U
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#define MSR_EMON_L3_CTR_CTL7 0x000107D3U
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#ifdef PROFILING_ON
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/* Core (and Goldmont) specific MSRs */
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