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hv: fix 'Expression is not Boolean'

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MISRA-C requires that the controlling expression of an if statement or
an iteration-statement shall be Boolean type.

v1 -> v2:
* update the U suffix of constant to let the type of operands
  to bit operations (&) is the same.
* update the type of 'i' from uint64_t to uint16_t in
  'profiling_set_control' since it is limited by phys_cpu_num,
  which is uint16_t.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Shiqing Gao
2018-11-07 14:14:49 +08:00
committed by wenlingz
parent 121454c4bd
commit b430b00a08
14 changed files with 33 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
hypervisor/dm/vpci/msi.c
View File

@@ -57,7 +57,7 @@ static int vmsi_remap(struct pci_vdev *vdev, bool enable)
/* Read the MSI capability structure from virtual device */
addrlo = pci_vdev_read_cfg_u32(vdev, capoff + PCIR_MSI_ADDR);
if (msgctrl & PCIM_MSICTRL_64BIT) {
if ((msgctrl & PCIM_MSICTRL_64BIT) != 0U) {
msgdata = pci_vdev_read_cfg_u16(vdev, capoff + PCIR_MSI_DATA_64BIT);
addrhi = pci_vdev_read_cfg_u32(vdev, capoff + PCIR_MSI_ADDR_HIGH);
} else {
@@ -82,7 +82,7 @@ static int vmsi_remap(struct pci_vdev *vdev, bool enable)
/* Update MSI Capability structure to physical device */
pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_ADDR, 0x4U, (uint32_t)info.pmsi_addr);
if (msgctrl & PCIM_MSICTRL_64BIT) {
if ((msgctrl & PCIM_MSICTRL_64BIT) != 0U) {
pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_ADDR_HIGH, 0x4U, (uint32_t)(info.pmsi_addr >> 32U));
pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_DATA_64BIT, 0x2U, (uint16_t)info.pmsi_data);
} else {
@@ -130,7 +130,8 @@ static int vmsi_cfgwrite(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes,
pci_vdev_write_cfg(vdev, offset, bytes, val);
/* Do remap if MSI Enable bit is being changed */
if (((offset - vdev->msi.capoff) == PCIR_MSI_CTRL) && ((msgctrl ^ val) & PCIM_MSICTRL_MSI_ENABLE)) {
if (((offset - vdev->msi.capoff) == PCIR_MSI_CTRL) &&
(((msgctrl ^ val) & PCIM_MSICTRL_MSI_ENABLE) != 0U)) {
enable = ((val & PCIM_MSICTRL_MSI_ENABLE) != 0U);
(void)vmsi_remap(vdev, enable);
} else {
@@ -173,7 +174,7 @@ void populate_msi_struct(struct pci_vdev *vdev)
* (msgctrl & PCIM_MSICTRL_VECTOR).
* We'll let the guest manipulate them directly.
*/
len = (msgctrl & PCIM_MSICTRL_64BIT) ? 14U : 10U;
len = ((msgctrl & PCIM_MSICTRL_64BIT) != 0U) ? 14U : 10U;
vdev->msi.caplen = len;
/* Assign MSI handler for configuration read and write */

2
hypervisor/dm/vpci/msix.c
View File

@@ -169,7 +169,7 @@ static int vmsix_cfgwrite(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes
/* Writing Message Control field? */
if ((offset - vdev->msix.capoff) == PCIR_MSIX_CTRL) {
if (((msgctrl ^ val) & PCIM_MSIXCTRL_MSIX_ENABLE) != 0U) {
if (val & PCIM_MSIXCTRL_MSIX_ENABLE) {
if ((val & PCIM_MSIXCTRL_MSIX_ENABLE) != 0U) {
(void)vmsix_remap(vdev, true);
} else {
(void)vmsix_remap(vdev, false);

5
hypervisor/dm/vpci/vpci.c
View File

@@ -45,7 +45,7 @@ static void pci_cfg_clear_cache(struct pci_addr_info *pi)
{
pi->cached_bdf.value = 0xFFFFU;
pi->cached_reg = 0U;
pi->cached_enable = 0U;
pi->cached_enable = false;
}
static uint32_t pci_cfg_io_read(struct acrn_vm *vm, uint16_t addr, size_t bytes)
@@ -96,8 +96,7 @@ static void pci_cfg_io_write(struct acrn_vm *vm, uint16_t addr, size_t bytes,
pi->cached_bdf.bits.f = (uint8_t)(val >> 8U) & PCI_FUNCMAX;
pi->cached_reg = val & PCI_REGMAX;
pi->cached_enable =
(val & PCI_CFG_ENABLE) == PCI_CFG_ENABLE;
pi->cached_enable = ((val & PCI_CFG_ENABLE) == PCI_CFG_ENABLE);
}
} else if (is_cfg_data(addr)) {
if (pi->cached_enable) {

4
hypervisor/dm/vpic.c
View File

@@ -411,7 +411,7 @@ static void vpic_set_pinstate(struct acrn_vpic *vpic, uint8_t pin,
i8259 = &vpic->i8259[pin >> 3U];
old_lvl = i8259->pin_state[pin & 0x7U];
if (level) {
if (level != 0U) {
i8259->pin_state[pin & 0x7U] = 1U;
} else {
i8259->pin_state[pin & 0x7U] = 0U;
@@ -432,7 +432,7 @@ static void vpic_set_pinstate(struct acrn_vpic *vpic, uint8_t pin,
}
} else {
dev_dbg(ACRN_DBG_PIC, "pic pin%hhu: %s, ignored\n",
pin, level ? "asserted" : "deasserted");
pin, (level != 0U) ? "asserted" : "deasserted");
}
vpic_notify_intr(vpic);