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hv: treewide: fix 'Prototype and definition name mismatch'

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Fix the parameter name mismatch between API declaration and definition.

v2 -> v3:
 * Fix two more violations which are missed in previous report.
   shell_puts and console_write

v1 -> v2:
 * Replace 'ret_desc' with 'desc'

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Shiqing Gao
2018-08-01 14:59:53 +08:00
committed by lijinxia
parent f42878ee3a
commit b4a2ff5022
17 changed files with 35 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
hypervisor/arch/x86/guest/instr_emul.c
View File

@@ -1484,14 +1484,14 @@ vmm_emulate_instruction(struct vcpu *vcpu, uint64_t gpa, struct instr_emul_vie *
}
int
vie_alignment_check(uint8_t cpl, uint8_t size, uint64_t cr0, uint64_t rf,
vie_alignment_check(uint8_t cpl, uint8_t size, uint64_t cr0, uint64_t rflags,
uint64_t gla)
{
ASSERT(size == 1U || size == 2U || size == 4U || size == 8U,
"%s: invalid size %hhu", __func__, size);
ASSERT(cpl <= 3U, "%s: invalid cpl %d", __func__, cpl);
if (cpl != 3U || (cr0 & CR0_AM) == 0UL || (rf & PSL_AC) == 0UL) {
if (cpl != 3U || (cr0 & CR0_AM) == 0UL || (rflags & PSL_AC) == 0UL) {
return 0;
}

6
hypervisor/arch/x86/guest/instr_emul.h
View File

@@ -45,7 +45,7 @@ typedef int (*mem_region_write_t)(struct vcpu *vcpu, uint64_t gpa,
* Emulate the decoded 'vie' instruction.
*
* The callbacks 'mrr' and 'mrw' emulate reads and writes to the memory region
* containing 'gpa'. 'mrarg' is an opaque argument that is passed into the
* containing 'gpa'. 'memarg' is an opaque argument that is passed into the
* callback functions.
*
* 'void *vm' should be 'struct vm *' when called from kernel context and
@@ -54,7 +54,7 @@ typedef int (*mem_region_write_t)(struct vcpu *vcpu, uint64_t gpa,
*/
int vmm_emulate_instruction(struct vcpu *vcpu, uint64_t gpa, struct instr_emul_vie *vie,
struct vm_guest_paging *paging, mem_region_read_t mrr,
mem_region_write_t mrw, void *mrarg);
mem_region_write_t mrw, void *memarg);
int vie_update_register(struct vcpu *vcpu, enum cpu_reg_name reg,
uint64_t val_arg, uint8_t size);
@@ -62,7 +62,7 @@ int vie_update_register(struct vcpu *vcpu, enum cpu_reg_name reg,
/*
* Returns 1 if an alignment check exception should be injected and 0 otherwise.
*/
int vie_alignment_check(uint8_t cpl, uint8_t operand_size, uint64_t cr0,
int vie_alignment_check(uint8_t cpl, uint8_t size, uint64_t cr0,
uint64_t rflags, uint64_t gla);
/* Returns 1 if the 'gla' is not canonical and 0 otherwise. */

10
hypervisor/arch/x86/guest/instr_emul_wrapper.c
View File

@@ -95,12 +95,12 @@ int vm_set_register(struct vcpu *vcpu, enum cpu_reg_name reg, uint64_t val)
}
int vm_set_seg_desc(struct vcpu *vcpu, enum cpu_reg_name seg,
struct seg_desc *ret_desc)
struct seg_desc *desc)
{
int error;
uint32_t base, limit, access;
if ((vcpu == NULL) || (ret_desc == NULL)) {
if ((vcpu == NULL) || (desc == NULL)) {
return -EINVAL;
}
@@ -113,9 +113,9 @@ int vm_set_seg_desc(struct vcpu *vcpu, enum cpu_reg_name seg,
return -EINVAL;
}
exec_vmwrite(base, ret_desc->base);
exec_vmwrite32(limit, ret_desc->limit);
exec_vmwrite32(access, ret_desc->access);
exec_vmwrite(base, desc->base);
exec_vmwrite32(limit, desc->limit);
exec_vmwrite32(access, desc->access);
return 0;
}

6
hypervisor/arch/x86/guest/instr_emul_wrapper.h
View File

@@ -251,8 +251,8 @@ struct instr_emul_ctxt {
int vm_get_register(struct vcpu *vcpu, enum cpu_reg_name reg, uint64_t *retval);
int vm_set_register(struct vcpu *vcpu, enum cpu_reg_name reg, uint64_t val);
int vm_get_seg_desc(struct vcpu *vcpu, enum cpu_reg_name reg,
struct seg_desc *ret_desc);
int vm_set_seg_desc(struct vcpu *vcpu, enum cpu_reg_name reg,
int vm_get_seg_desc(struct vcpu *vcpu, enum cpu_reg_name seg,
struct seg_desc *desc);
int vm_set_seg_desc(struct vcpu *vcpu, enum cpu_reg_name seg,
struct seg_desc *desc);
#endif

12
hypervisor/arch/x86/guest/vlapic.c
View File

@@ -1978,7 +1978,7 @@ vlapic_rdmsr(struct vcpu *vcpu, uint32_t msr, uint64_t *rval)
}
int
vlapic_wrmsr(struct vcpu *vcpu, uint32_t msr, uint64_t val)
vlapic_wrmsr(struct vcpu *vcpu, uint32_t msr, uint64_t wval)
{
int error = 0;
uint32_t offset;
@@ -1988,21 +1988,21 @@ vlapic_wrmsr(struct vcpu *vcpu, uint32_t msr, uint64_t val)
switch (msr) {
case MSR_IA32_APIC_BASE:
error = vlapic_set_apicbase(vlapic, val);
error = vlapic_set_apicbase(vlapic, wval);
break;
case MSR_IA32_TSC_DEADLINE:
vlapic_set_tsc_deadline_msr(vlapic, val);
vlapic_set_tsc_deadline_msr(vlapic, wval);
break;
default:
offset = x2apic_msr_to_regoff(msr);
error = vlapic_write(vlapic, 0, offset, val);
error = vlapic_write(vlapic, 0, offset, wval);
break;
}
dev_dbg(ACRN_DBG_LAPIC, "cpu[%hu] wrmsr: %x val=%#x",
vcpu->vcpu_id, msr, val);
dev_dbg(ACRN_DBG_LAPIC, "cpu[%hu] wrmsr: %x wval=%#x",
vcpu->vcpu_id, msr, wval);
return error;
}

2
hypervisor/arch/x86/vtd.c
View File

@@ -172,7 +172,7 @@ static spinlock_t domain_lock;
static struct iommu_domain *host_domain;
static struct list_head iommu_domains;
static void dmar_register_hrhd(struct dmar_drhd_rt *drhd_rt);
static void dmar_register_hrhd(struct dmar_drhd_rt *dmar_uint);
static struct dmar_drhd_rt *device_to_dmaru(uint16_t segment, uint8_t bus,
uint8_t devfun);
static void register_hrhd_units(void)