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hv: iommu: disable snoop bit in EPT-PTE/SL-PTE

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Due to the fact that i915 iommu doesn't support snoop, hence it can't
access memory when the SNOOP bit of Secondary Level page PTE (SL-PTE)
is set, this will cause many undefined issues such as invisible cursor
in WaaG etc.

Current hv design uses EPT as Scondary Leval Page for iommu, and this
patch removes the codes of setting SNOOP bit in both EPT-PTE and SL-PTE
to avoid errors.

And according to SDM 28.2.2, the SNOOP bit (11th bit) will be ignored
by EPT, so it will not affect the CPU address translation.

Tracked-On: #4509
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
This commit is contained in:
Xiaoguang Wu 2020-03-26 15:17:18 +08:00 committed by wenlingz
parent 4b1dfe9632
commit b4f1e5aa85
1 changed files with 0 additions and 12 deletions
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12
hypervisor/arch/x86/guest/ept.c
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@ -116,14 +116,6 @@ void ept_add_mr(struct acrn_vm *vm, uint64_t *pml4_page,
dev_dbg(DBG_LEVEL_EPT, "%s, vm[%d] hpa: 0x%016lx gpa: 0x%016lx size: 0x%016lx prot: 0x%016x\n",
__func__, vm->vm_id, hpa, gpa, size, prot);
/* EPT & VT-d share the same page tables, set SNP bit
* to force snooping of PCIe devices if the page
* is cachable
*/
if (((prot & EPT_MT_MASK) != EPT_UNCACHED) && iommu_snoop_supported(vm->iommu)) {
prot |= EPT_SNOOP_CTRL;
}
spinlock_obtain(&vm->ept_lock);
mmu_add(pml4_page, hpa, gpa, size, prot, &vm->arch_vm.ept_mem_ops);
@ -145,10 +137,6 @@ void ept_modify_mr(struct acrn_vm *vm, uint64_t *pml4_page,
dev_dbg(DBG_LEVEL_EPT, "%s,vm[%d] gpa 0x%lx size 0x%lx\n", __func__, vm->vm_id, gpa, size);
if (((local_prot & EPT_MT_MASK) != EPT_UNCACHED) && iommu_snoop_supported(vm->iommu)) {
local_prot |= EPT_SNOOP_CTRL;
}
spinlock_obtain(&vm->ept_lock);
mmu_modify_or_del(pml4_page, gpa, size, local_prot, prot_clr, &(vm->arch_vm.ept_mem_ops), MR_MODIFY);