github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-06-19 12:12:16 +00:00
Code Issues Projects Releases Wiki Activity

hv: Hide HLAT to guest

Browse Source 
For platform with HLAT (Hypervisor-managed Linear Address Translation)
capability, the hypervisor shall hide this feature to its guest.

This patch adds MSR_IA32_VMX_PROCBASED_CTLS3 MSR to unsupported MSR
list.

The presence of this MSR is determined by 1-setting of bit 49 of MSR
MSR_IA32_VMX_PROCBASED_CTLS. which is already in unsupported MSR list. [2]

Related documentations:
[1] Intel Architecture Instruction Set Extensions, version Feb 16, 2021,
Ch 6.12
[2] Intel KeyLocker Specification, Sept 2020, Ch 7.2

Tracked-On: #5895
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Yifan Liu 2021-03-19 14:15:07 +08:00 committed by wenlingz
parent 14e9367cd5
commit b80c388b52
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hypervisor/arch/x86/guest/vmsr.c
View File

@ -89,7 +89,7 @@ static const uint32_t mtrr_msrs[NUM_MTRR_MSRS] = {
}; };
/* Following MSRs are intercepted, but it throws GPs for any guest accesses */ /* Following MSRs are intercepted, but it throws GPs for any guest accesses */
#define NUM_UNSUPPORTED_MSRS 111U #define NUM_UNSUPPORTED_MSRS 112U
static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = { static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
/* Variable MTRRs are not supported */ /* Variable MTRRs are not supported */
MSR_IA32_MTRR_PHYSBASE_0, MSR_IA32_MTRR_PHYSBASE_0,
@ -135,6 +135,7 @@ static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
MSR_IA32_VMX_TRUE_EXIT_CTLS, MSR_IA32_VMX_TRUE_EXIT_CTLS,
MSR_IA32_VMX_TRUE_ENTRY_CTLS, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
MSR_IA32_VMX_VMFUNC, MSR_IA32_VMX_VMFUNC,
MSR_IA32_VMX_PROCBASED_CTLS3,
/* MPX disabled: CPUID.07H.EBX[14] */ /* MPX disabled: CPUID.07H.EBX[14] */
MSR_IA32_BNDCFGS, MSR_IA32_BNDCFGS,