Patch for modularising ioapic.[c/h] and related files.

This adds few functions to access the daata structures
defined inside ioapic.c. Removes the same data structures
from ioapic.h
Also this modifies some of the names of existing APIs to
conform to the ioapic module name.
Modified gsi_table identifier to gs_table_data, to avoid
a MISRA C Violation.

Tracked-On: #1842
Signed-off-by: Arindam Roy <arindam.roy@intel.com>
This commit is contained in:
Arindam Roy
2018-12-20 16:05:55 -08:00
committed by wenlingz
parent af9b747629
commit bec21d147b
8 changed files with 118 additions and 77 deletions

View File

@@ -5,12 +5,20 @@
*/
#include <hypervisor.h>
#include <ioapic.h>
#define IOAPIC_MAX_PIN 240U
#define IOAPIC_INVALID_PIN 0xffU
struct gsi_table gsi_table[NR_MAX_GSI];
uint32_t nr_gsi;
/*
* IOAPIC_MAX_LINES is architecturally defined.
* The usable RTEs may be a subset of the total on a per IO APIC basis.
*/
#define IOAPIC_MAX_LINES 120U
#define NR_MAX_GSI (NR_IOAPICS * IOAPIC_MAX_LINES)
static struct gsi_table gsi_table_data[NR_MAX_GSI];
static uint32_t ioapic_nr_gsi;
static spinlock_t ioapic_lock;
static union ioapic_rte saved_rte[NR_IOAPICS][IOAPIC_MAX_PIN];
@@ -76,6 +84,26 @@ const uint8_t pic_ioapic_pin_map[NR_LEGACY_PIN] = {
15U, /* pin15*/
};
uint8_t get_pic_pin_from_ioapic_pin (uint8_t pin_index) {
uint8_t pin_id = IOAPIC_INVALID_PIN;
if (pin_index < NR_LEGACY_PIN) {
pin_id = pic_ioapic_pin_map[pin_index];
}
return pin_id;
}
void *ioapic_get_gsi_irq_addr (uint32_t irq_num) {
void *addr = NULL;
if (irq_num < NR_MAX_GSI) {
addr = gsi_table_data[irq_num].addr;
}
return addr;
}
uint32_t ioapic_get_nr_gsi (void) {
return ioapic_nr_gsi;
}
static void *map_ioapic(uint64_t ioapic_paddr)
{
/* At some point we may need to translate this paddr to a vaddr.
@@ -199,9 +227,9 @@ static void ioapic_set_routing(uint32_t gsi, uint32_t vr)
void *addr;
union ioapic_rte rte;
addr = gsi_table[gsi].addr;
addr = gsi_table_data[gsi].addr;
rte = create_rte_for_gsi_irq(gsi, vr);
ioapic_set_rte_entry(addr, gsi_table[gsi].pin, rte);
ioapic_set_rte_entry(addr, gsi_table_data[gsi].pin, rte);
if ((rte.full & IOAPIC_RTE_TRGRMOD) != 0UL) {
set_irq_trigger_mode(gsi, true);
@@ -210,7 +238,7 @@ static void ioapic_set_routing(uint32_t gsi, uint32_t vr)
}
dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",
gsi, gsi_table[gsi].pin,
gsi, gsi_table_data[gsi].pin,
rte.full);
}
@@ -221,9 +249,9 @@ void ioapic_get_rte(uint32_t irq, union ioapic_rte *rte)
{
void *addr;
if (irq_is_gsi(irq)) {
addr = gsi_table[irq].addr;
ioapic_get_rte_entry(addr, gsi_table[irq].pin, rte);
if (ioapic_irq_is_gsi(irq)) {
addr = gsi_table_data[irq].addr;
ioapic_get_rte_entry(addr, gsi_table_data[irq].pin, rte);
}
}
@@ -231,27 +259,27 @@ void ioapic_set_rte(uint32_t irq, union ioapic_rte rte)
{
void *addr;
if (irq_is_gsi(irq)) {
addr = gsi_table[irq].addr;
ioapic_set_rte_entry(addr, gsi_table[irq].pin, rte);
if (ioapic_irq_is_gsi(irq)) {
addr = gsi_table_data[irq].addr;
ioapic_set_rte_entry(addr, gsi_table_data[irq].pin, rte);
dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",
irq, gsi_table[irq].pin,
irq, gsi_table_data[irq].pin,
rte.full);
}
}
bool irq_is_gsi(uint32_t irq)
bool ioapic_irq_is_gsi(uint32_t irq)
{
return irq < nr_gsi;
return irq < ioapic_nr_gsi;
}
uint8_t irq_to_pin(uint32_t irq)
uint8_t ioapic_irq_to_pin(uint32_t irq)
{
uint8_t ret;
if (irq_is_gsi(irq)) {
ret = gsi_table[irq].pin;
if (ioapic_irq_is_gsi(irq)) {
ret = gsi_table_data[irq].pin;
} else {
ret = IOAPIC_INVALID_PIN;
}
@@ -259,13 +287,17 @@ uint8_t irq_to_pin(uint32_t irq)
return ret;
}
uint32_t pin_to_irq(uint8_t pin)
bool ioapic_is_pin_valid (uint8_t pin) {
return (pin != IOAPIC_INVALID_PIN);
}
uint32_t ioapic_pin_to_irq(uint8_t pin)
{
uint32_t i;
uint32_t irq = IRQ_INVALID;
for (i = 0U; i < nr_gsi; i++) {
if (gsi_table[i].pin == pin) {
for (i = 0U; i < ioapic_nr_gsi; i++) {
if (gsi_table_data[i].pin == pin) {
irq = i;
break;
}
@@ -274,36 +306,40 @@ uint32_t pin_to_irq(uint8_t pin)
}
static void
irq_gsi_mask_unmask(uint32_t irq, bool mask)
ioapic_irq_gsi_mask_unmask(uint32_t irq, bool mask)
{
void *addr;
void *addr = NULL;
uint8_t pin;
union ioapic_rte rte;
if (irq_is_gsi(irq)) {
addr = gsi_table[irq].addr;
pin = gsi_table[irq].pin;
if (ioapic_irq_is_gsi(irq)) {
addr = gsi_table_data[irq].addr;
pin = gsi_table_data[irq].pin;
ioapic_get_rte_entry(addr, pin, &rte);
if (mask) {
rte.full |= IOAPIC_RTE_INTMSET;
if (addr != NULL) {
ioapic_get_rte_entry(addr, pin, &rte);
if (mask) {
rte.full |= IOAPIC_RTE_INTMSET;
} else {
rte.full &= ~IOAPIC_RTE_INTMASK;
}
ioapic_set_rte_entry(addr, pin, rte);
dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%hhu rte:%lx",
irq, pin, rte.full);
} else {
rte.full &= ~IOAPIC_RTE_INTMASK;
dev_dbg(ACRN_DBG_PTIRQ, "NULL Address returned from gsi_table_data");
}
ioapic_set_rte_entry(addr, pin, rte);
dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%hhu rte:%lx",
irq, pin, rte.full);
}
}
void gsi_mask_irq(uint32_t irq)
void ioapic_gsi_mask_irq(uint32_t irq)
{
irq_gsi_mask_unmask(irq, true);
ioapic_irq_gsi_mask_unmask(irq, true);
}
void gsi_unmask_irq(uint32_t irq)
void ioapic_gsi_unmask_irq(uint32_t irq)
{
irq_gsi_mask_unmask(irq, false);
ioapic_irq_gsi_mask_unmask(irq, false);
}
static uint8_t
@@ -327,7 +363,7 @@ ioapic_nr_pins(void *ioapic_base)
return nr_pins;
}
void setup_ioapic_irqs(void)
void ioapic_setup_irqs(void)
{
uint8_t ioapic_id;
uint32_t gsi = 0U;
@@ -345,14 +381,14 @@ void setup_ioapic_irqs(void)
nr_pins = ioapic_nr_pins(addr);
for (pin = 0U; pin < nr_pins; pin++) {
gsi_table[gsi].ioapic_id = ioapic_id;
gsi_table[gsi].addr = addr;
gsi_table_data[gsi].ioapic_id = ioapic_id;
gsi_table_data[gsi].addr = addr;
if (gsi < NR_LEGACY_IRQ) {
gsi_table[gsi].pin =
gsi_table_data[gsi].pin =
legacy_irq_to_pin[gsi] & 0xffU;
} else {
gsi_table[gsi].pin = pin;
gsi_table_data[gsi].pin = pin;
}
/* pinned irq before use it */
@@ -382,8 +418,8 @@ void setup_ioapic_irqs(void)
}
/* system max gsi numbers */
nr_gsi = gsi;
ASSERT(nr_gsi <= NR_MAX_GSI, "GSI table overflow");
ioapic_nr_gsi = gsi;
ASSERT(ioapic_nr_gsi <= NR_MAX_GSI, "GSI table overflow");
}
void suspend_ioapic(void)