mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-21 21:19:35 +00:00
hv: irq: fix "Procedure has more than one exit point"
IEC 61508,ISO 26262 standards highly recommend single-exit rule. Reduce the count of the "return entries". Fix the violations which is comply with the cases list below: 1.Function has 2 return entries. 2.The first return entry is used to return the error code of checking variable whether is valid. Fix the violations in "if else" format. Tracked-On: #861 Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Huihuang Shi
lijinxia
parent
8dfb9bd9c0
commit
c32d41a0be
@ -176,22 +176,22 @@ create_rte_for_gsi_irq(uint32_t irq, uint32_t vr)
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union ioapic_rte rte;
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if (irq < NR_LEGACY_IRQ) {
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return create_rte_for_legacy_irq(irq, vr);
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rte = create_rte_for_legacy_irq(irq, vr);
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} else {
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/* irq default masked, level trig */
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rte.full = IOAPIC_RTE_INTMSET;
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rte.full |= IOAPIC_RTE_TRGRLVL;
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rte.full |= DEFAULT_DEST_MODE;
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rte.full |= DEFAULT_DELIVERY_MODE;
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rte.full |= (IOAPIC_RTE_INTVEC & (uint64_t)vr);
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/* Fixed to active high */
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rte.full |= IOAPIC_RTE_INTAHI;
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/* Dest field */
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rte.full |= ((uint64_t)ALL_CPUS_MASK << IOAPIC_RTE_DEST_SHIFT);
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}
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/* irq default masked, level trig */
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rte.full = IOAPIC_RTE_INTMSET;
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rte.full |= IOAPIC_RTE_TRGRLVL;
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rte.full |= DEFAULT_DEST_MODE;
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rte.full |= DEFAULT_DELIVERY_MODE;
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rte.full |= (IOAPIC_RTE_INTVEC & (uint64_t)vr);
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/* Fixed to active high */
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rte.full |= IOAPIC_RTE_INTAHI;
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/* Dest field */
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rte.full |= ((uint64_t)ALL_CPUS_MASK << IOAPIC_RTE_DEST_SHIFT);
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return rte;
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}
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@ -222,28 +222,24 @@ void ioapic_get_rte(uint32_t irq, union ioapic_rte *rte)
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{
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void *addr;
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if (!irq_is_gsi(irq)) {
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return;
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if (irq_is_gsi(irq)) {
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addr = gsi_table[irq].addr;
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ioapic_get_rte_entry(addr, gsi_table[irq].pin, rte);
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}
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addr = gsi_table[irq].addr;
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ioapic_get_rte_entry(addr, gsi_table[irq].pin, rte);
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}
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void ioapic_set_rte(uint32_t irq, union ioapic_rte rte)
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{
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void *addr;
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if (!irq_is_gsi(irq)) {
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return;
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if (irq_is_gsi(irq)) {
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addr = gsi_table[irq].addr;
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ioapic_set_rte_entry(addr, gsi_table[irq].pin, rte);
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dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",
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irq, gsi_table[irq].pin,
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rte.full);
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}
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addr = gsi_table[irq].addr;
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ioapic_set_rte_entry(addr, gsi_table[irq].pin, rte);
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dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",
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irq, gsi_table[irq].pin,
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rte.full);
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}
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bool irq_is_gsi(uint32_t irq)
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@ -253,11 +249,15 @@ bool irq_is_gsi(uint32_t irq)
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uint8_t irq_to_pin(uint32_t irq)
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{
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uint8_t ret;
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if (irq_is_gsi(irq)) {
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return gsi_table[irq].pin;
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ret = gsi_table[irq].pin;
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} else {
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return IOAPIC_INVALID_PIN;
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ret = IOAPIC_INVALID_PIN;
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}
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return ret;
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}
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uint32_t pin_to_irq(uint8_t pin)
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@ -279,22 +279,20 @@ irq_gsi_mask_unmask(uint32_t irq, bool mask)
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uint8_t pin;
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union ioapic_rte rte;
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if (!irq_is_gsi(irq)) {
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return;
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}
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if (irq_is_gsi(irq)) {
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addr = gsi_table[irq].addr;
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pin = gsi_table[irq].pin;
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addr = gsi_table[irq].addr;
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pin = gsi_table[irq].pin;
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ioapic_get_rte_entry(addr, pin, &rte);
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if (mask) {
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rte.full |= IOAPIC_RTE_INTMSET;
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} else {
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rte.full &= ~IOAPIC_RTE_INTMASK;
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ioapic_get_rte_entry(addr, pin, &rte);
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if (mask) {
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rte.full |= IOAPIC_RTE_INTMSET;
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} else {
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rte.full &= ~IOAPIC_RTE_INTMASK;
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}
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ioapic_set_rte_entry(addr, pin, rte);
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dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%hhu rte:%lx",
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irq, pin, rte.full);
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}
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ioapic_set_rte_entry(addr, pin, rte);
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dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%hhu rte:%lx",
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irq, pin, rte.full);
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}
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void gsi_mask_irq(uint32_t irq)
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@ -36,26 +36,28 @@ uint32_t alloc_irq_num(uint32_t req_irq)
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{
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uint32_t irq = req_irq;
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uint64_t rflags;
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uint32_t ret;
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if ((irq >= NR_IRQS) && (irq != IRQ_INVALID)) {
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pr_err("[%s] invalid req_irq %u", __func__, req_irq);
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return IRQ_INVALID;
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}
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spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
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if (irq == IRQ_INVALID) {
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/* if no valid irq num given, find a free one */
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irq = (uint32_t)ffz64_ex(irq_alloc_bitmap, NR_IRQS);
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}
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if (irq >= NR_IRQS) {
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irq = IRQ_INVALID;
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ret = IRQ_INVALID;
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} else {
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bitmap_set_nolock((uint16_t)(irq & 0x3FU),
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irq_alloc_bitmap + (irq >> 6U));
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spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
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if (irq == IRQ_INVALID) {
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/* if no valid irq num given, find a free one */
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irq = (uint32_t)ffz64_ex(irq_alloc_bitmap, NR_IRQS);
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}
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if (irq >= NR_IRQS) {
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irq = IRQ_INVALID;
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} else {
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bitmap_set_nolock((uint16_t)(irq & 0x3FU),
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irq_alloc_bitmap + (irq >> 6U));
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}
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spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
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ret = irq;
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}
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spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
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return irq;
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return ret;
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}
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/*
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@ -66,15 +68,13 @@ void free_irq_num(uint32_t irq)
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{
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uint64_t rflags;
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if (irq >= NR_IRQS) {
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return;
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}
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if (irq_is_gsi(irq) == false) {
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spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
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(void)bitmap_test_and_clear_nolock((uint16_t)(irq & 0x3FU),
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irq_alloc_bitmap + (irq >> 6U));
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spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
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if (irq < NR_IRQS) {
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if (!irq_is_gsi(irq)) {
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spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
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(void)bitmap_test_and_clear_nolock((uint16_t)(irq & 0x3FU),
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irq_alloc_bitmap + (irq >> 6U));
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spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
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}
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}
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}
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@ -89,43 +89,44 @@ uint32_t alloc_irq_vector(uint32_t irq)
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uint32_t vr;
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struct irq_desc *desc;
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uint64_t rflags;
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uint32_t ret;
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if (irq >= NR_IRQS) {
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pr_err("invalid irq[%u] to alloc vector", irq);
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return VECTOR_INVALID;
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}
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if (irq < NR_IRQS) {
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desc = &irq_desc_array[irq];
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desc = &irq_desc_array[irq];
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if (desc->vector != VECTOR_INVALID) {
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if (vector_to_irq[desc->vector] == irq) {
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/* statically binded */
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vr = desc->vector;
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} else {
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pr_err("[%s] irq[%u]:vector[%u] mismatch",
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__func__, irq, desc->vector);
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vr = VECTOR_INVALID;
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}
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} else {
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/* alloc a vector between:
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* VECTOR_DYNAMIC_START ~ VECTOR_DYNAMC_END
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*/
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spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
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for (vr = VECTOR_DYNAMIC_START;
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vr <= VECTOR_DYNAMIC_END; vr++) {
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if (vector_to_irq[vr] == IRQ_INVALID) {
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desc->vector = vr;
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vector_to_irq[vr] = irq;
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break;
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if (desc->vector != VECTOR_INVALID) {
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if (vector_to_irq[desc->vector] == irq) {
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/* statically binded */
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vr = desc->vector;
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} else {
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pr_err("[%s] irq[%u]:vector[%u] mismatch",
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__func__, irq, desc->vector);
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vr = VECTOR_INVALID;
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}
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} else {
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/* alloc a vector between:
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* VECTOR_DYNAMIC_START ~ VECTOR_DYNAMC_END
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*/
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spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
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for (vr = VECTOR_DYNAMIC_START;
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vr <= VECTOR_DYNAMIC_END; vr++) {
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if (vector_to_irq[vr] == IRQ_INVALID) {
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desc->vector = vr;
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vector_to_irq[vr] = irq;
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break;
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}
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}
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vr = (vr > VECTOR_DYNAMIC_END) ? VECTOR_INVALID : vr;
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spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
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}
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vr = (vr > VECTOR_DYNAMIC_END) ? VECTOR_INVALID : vr;
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spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
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ret = vr;
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} else {
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pr_err("invalid irq[%u] to alloc vector", irq);
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ret = VECTOR_INVALID;
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}
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return vr;
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return ret;
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}
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/* free the vector allocated via alloc_irq_vector() */
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@ -226,22 +227,20 @@ void free_irq(uint32_t irq)
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uint64_t rflags;
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struct irq_desc *desc;
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if (irq >= NR_IRQS) {
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return;
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if (irq < NR_IRQS) {
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desc = &irq_desc_array[irq];
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dev_dbg(ACRN_DBG_IRQ, "[%s] irq%d vr:0x%x",
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__func__, irq, irq_to_vector(irq));
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free_irq_vector(irq);
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free_irq_num(irq);
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spinlock_irqsave_obtain(&desc->lock, &rflags);
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desc->action = NULL;
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desc->priv_data = NULL;
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desc->flags = IRQF_NONE;
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spinlock_irqrestore_release(&desc->lock, rflags);
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}
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desc = &irq_desc_array[irq];
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dev_dbg(ACRN_DBG_IRQ, "[%s] irq%d vr:0x%x",
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__func__, irq, irq_to_vector(irq));
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free_irq_vector(irq);
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free_irq_num(irq);
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spinlock_irqsave_obtain(&desc->lock, &rflags);
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desc->action = NULL;
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desc->priv_data = NULL;
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desc->flags = IRQF_NONE;
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spinlock_irqrestore_release(&desc->lock, rflags);
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}
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void set_irq_trigger_mode(uint32_t irq, bool is_level_triggered)
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@ -249,27 +248,28 @@ void set_irq_trigger_mode(uint32_t irq, bool is_level_triggered)
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uint64_t rflags;
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struct irq_desc *desc;
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if (irq >= NR_IRQS) {
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return;
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if (irq < NR_IRQS) {
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desc = &irq_desc_array[irq];
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spinlock_irqsave_obtain(&desc->lock, &rflags);
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if (is_level_triggered == true) {
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desc->flags |= IRQF_LEVEL;
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} else {
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desc->flags &= ~IRQF_LEVEL;
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}
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spinlock_irqrestore_release(&desc->lock, rflags);
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}
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desc = &irq_desc_array[irq];
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spinlock_irqsave_obtain(&desc->lock, &rflags);
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if (is_level_triggered == true) {
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desc->flags |= IRQF_LEVEL;
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} else {
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desc->flags &= ~IRQF_LEVEL;
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}
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spinlock_irqrestore_release(&desc->lock, rflags);
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}
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uint32_t irq_to_vector(uint32_t irq)
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{
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uint32_t ret;
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if (irq < NR_IRQS) {
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return irq_desc_array[irq].vector;
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ret = irq_desc_array[irq].vector;
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} else {
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return VECTOR_INVALID;
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ret = VECTOR_INVALID;
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}
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return ret;
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}
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static void handle_spurious_interrupt(uint32_t vector)
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@ -435,16 +435,14 @@ static void disable_pic_irqs(void)
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void init_default_irqs(uint16_t cpu_id)
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{
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if (cpu_id != BOOT_CPU_ID) {
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return;
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if (cpu_id == BOOT_CPU_ID) {
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init_irq_descs();
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/* we use ioapic only, disable legacy PIC */
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disable_pic_irqs();
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setup_ioapic_irqs();
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init_softirq();
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}
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init_irq_descs();
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/* we use ioapic only, disable legacy PIC */
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disable_pic_irqs();
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setup_ioapic_irqs();
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init_softirq();
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}
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void interrupt_init(uint16_t pcpu_id)
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