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hv: irq: fix "Procedure has more than one exit point"

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IEC 61508,ISO 26262 standards highly recommend single-exit rule.

Reduce the count of the "return entries".
Fix the violations which is comply with the cases list below:
1.Function has 2 return entries.
2.The first return entry is used to return the error code of
checking variable whether is valid.

Fix the violations in "if else" format.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Huihuang Shi 2018-11-28 10:23:59 +08:00 committed by lijinxia
parent 8dfb9bd9c0
commit c32d41a0be
2 changed files with 133 additions and 137 deletions
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32
hypervisor/arch/x86/ioapic.c
View File

@ -176,9 +176,8 @@ create_rte_for_gsi_irq(uint32_t irq, uint32_t vr)
union ioapic_rte rte;
if (irq < NR_LEGACY_IRQ) {
return create_rte_for_legacy_irq(irq, vr);
}
rte = create_rte_for_legacy_irq(irq, vr);
} else {
/* irq default masked, level trig */
rte.full = IOAPIC_RTE_INTMSET;
rte.full |= IOAPIC_RTE_TRGRLVL;
@ -191,6 +190,7 @@ create_rte_for_gsi_irq(uint32_t irq, uint32_t vr)
/* Dest field */
rte.full |= ((uint64_t)ALL_CPUS_MASK << IOAPIC_RTE_DEST_SHIFT);
}
return rte;
}
@ -222,22 +222,17 @@ void ioapic_get_rte(uint32_t irq, union ioapic_rte *rte)
{
void *addr;
if (!irq_is_gsi(irq)) {
return;
}
if (irq_is_gsi(irq)) {
addr = gsi_table[irq].addr;
ioapic_get_rte_entry(addr, gsi_table[irq].pin, rte);
}
}
void ioapic_set_rte(uint32_t irq, union ioapic_rte rte)
{
void *addr;
if (!irq_is_gsi(irq)) {
return;
}
if (irq_is_gsi(irq)) {
addr = gsi_table[irq].addr;
ioapic_set_rte_entry(addr, gsi_table[irq].pin, rte);
@ -245,6 +240,7 @@ void ioapic_set_rte(uint32_t irq, union ioapic_rte rte)
irq, gsi_table[irq].pin,
rte.full);
}
}
bool irq_is_gsi(uint32_t irq)
{
@ -253,11 +249,15 @@ bool irq_is_gsi(uint32_t irq)
uint8_t irq_to_pin(uint32_t irq)
{
uint8_t ret;
if (irq_is_gsi(irq)) {
return gsi_table[irq].pin;
ret = gsi_table[irq].pin;
} else {
return IOAPIC_INVALID_PIN;
ret = IOAPIC_INVALID_PIN;
}
return ret;
}
uint32_t pin_to_irq(uint8_t pin)
@ -279,10 +279,7 @@ irq_gsi_mask_unmask(uint32_t irq, bool mask)
uint8_t pin;
union ioapic_rte rte;
if (!irq_is_gsi(irq)) {
return;
}
if (irq_is_gsi(irq)) {
addr = gsi_table[irq].addr;
pin = gsi_table[irq].pin;
@ -296,6 +293,7 @@ irq_gsi_mask_unmask(uint32_t irq, bool mask)
dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%hhu rte:%lx",
irq, pin, rte.full);
}
}
void gsi_mask_irq(uint32_t irq)
{

58
hypervisor/arch/x86/irq.c
View File

@ -36,12 +36,12 @@ uint32_t alloc_irq_num(uint32_t req_irq)
{
uint32_t irq = req_irq;
uint64_t rflags;
uint32_t ret;
if ((irq >= NR_IRQS) && (irq != IRQ_INVALID)) {
pr_err("[%s] invalid req_irq %u", __func__, req_irq);
return IRQ_INVALID;
}
ret = IRQ_INVALID;
} else {
spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
if (irq == IRQ_INVALID) {
/* if no valid irq num given, find a free one */
@ -55,7 +55,9 @@ uint32_t alloc_irq_num(uint32_t req_irq)
irq_alloc_bitmap + (irq >> 6U));
}
spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
return irq;
ret = irq;
}
return ret;
}
/*
@ -66,17 +68,15 @@ void free_irq_num(uint32_t irq)
{
uint64_t rflags;
if (irq >= NR_IRQS) {
return;
}
if (irq_is_gsi(irq) == false) {
if (irq < NR_IRQS) {
if (!irq_is_gsi(irq)) {
spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
(void)bitmap_test_and_clear_nolock((uint16_t)(irq & 0x3FU),
irq_alloc_bitmap + (irq >> 6U));
spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
}
}
}
/*
* alloc an vectror and bind it to irq
@ -89,12 +89,9 @@ uint32_t alloc_irq_vector(uint32_t irq)
uint32_t vr;
struct irq_desc *desc;
uint64_t rflags;
uint32_t ret;
if (irq >= NR_IRQS) {
pr_err("invalid irq[%u] to alloc vector", irq);
return VECTOR_INVALID;
}
if (irq < NR_IRQS) {
desc = &irq_desc_array[irq];
if (desc->vector != VECTOR_INVALID) {
@ -124,8 +121,12 @@ uint32_t alloc_irq_vector(uint32_t irq)
spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
}
return vr;
ret = vr;
} else {
pr_err("invalid irq[%u] to alloc vector", irq);
ret = VECTOR_INVALID;
}
return ret;
}
/* free the vector allocated via alloc_irq_vector() */
@ -226,10 +227,7 @@ void free_irq(uint32_t irq)
uint64_t rflags;
struct irq_desc *desc;
if (irq >= NR_IRQS) {
return;
}
if (irq < NR_IRQS) {
desc = &irq_desc_array[irq];
dev_dbg(ACRN_DBG_IRQ, "[%s] irq%d vr:0x%x",
__func__, irq, irq_to_vector(irq));
@ -243,16 +241,14 @@ void free_irq(uint32_t irq)
desc->flags = IRQF_NONE;
spinlock_irqrestore_release(&desc->lock, rflags);
}
}
void set_irq_trigger_mode(uint32_t irq, bool is_level_triggered)
{
uint64_t rflags;
struct irq_desc *desc;
if (irq >= NR_IRQS) {
return;
}
if (irq < NR_IRQS) {
desc = &irq_desc_array[irq];
spinlock_irqsave_obtain(&desc->lock, &rflags);
if (is_level_triggered == true) {
@ -262,14 +258,18 @@ void set_irq_trigger_mode(uint32_t irq, bool is_level_triggered)
}
spinlock_irqrestore_release(&desc->lock, rflags);
}
}
uint32_t irq_to_vector(uint32_t irq)
{
uint32_t ret;
if (irq < NR_IRQS) {
return irq_desc_array[irq].vector;
ret = irq_desc_array[irq].vector;
} else {
return VECTOR_INVALID;
ret = VECTOR_INVALID;
}
return ret;
}
static void handle_spurious_interrupt(uint32_t vector)
@ -435,10 +435,7 @@ static void disable_pic_irqs(void)
void init_default_irqs(uint16_t cpu_id)
{
if (cpu_id != BOOT_CPU_ID) {
return;
}
if (cpu_id == BOOT_CPU_ID) {
init_irq_descs();
/* we use ioapic only, disable legacy PIC */
@ -446,6 +443,7 @@ void init_default_irqs(uint16_t cpu_id)
setup_ioapic_irqs();
init_softirq();
}
}
void interrupt_init(uint16_t pcpu_id)
{