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HV: add formated nuc7i7dnb configurations code in misc/vm_configs

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Add acrn-config tool formated nuc7i7dnb configurations code in misc/vm_configs/
folder with new layout;

Tracked-On: #5077

Signed-off-by: Victor Sun <victor.sun@intel.com>
This commit is contained in:
Victor Sun 2020-07-24 10:53:40 +08:00 committed by wenlingz
parent a57a4fd7fb
commit c5bd227f5b
20 changed files with 407 additions and 212 deletions
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94
misc/vm_configs/boards/nuc7i7dnb/board.c
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@ -1,53 +1,67 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* BIOS Information
* Vendor: Intel Corp.
* Version: DNKBLi7v.86A.0065.2019.0611.1424
* Release Date: 06/11/2019
* BIOS Revision: 5.6
*
* Base Board Information
* Manufacturer: Intel Corporation
* Product Name: NUC7i7DNB
* Version: J83500-204
*/
#include <board.h>
#include <vtd.h>
#include <msr.h>
#include <pci.h>
static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = {
{
.type = DRHD0_DEVSCOPE0_TYPE,
.id = DRHD0_DEVSCOPE0_ID,
.bus = DRHD0_DEVSCOPE0_BUS,
.devfun = DRHD0_DEVSCOPE0_PATH
.type = DRHD0_DEVSCOPE0_TYPE,
.id = DRHD0_DEVSCOPE0_ID,
.bus = DRHD0_DEVSCOPE0_BUS,
.devfun = DRHD0_DEVSCOPE0_PATH,
},
};
static struct dmar_dev_scope drhd1_dev_scope[DRHD1_DEV_CNT] = {
{
.type = DRHD1_DEVSCOPE0_TYPE,
.id = DRHD1_DEVSCOPE0_ID,
.bus = DRHD1_DEVSCOPE0_BUS,
.devfun = DRHD1_DEVSCOPE0_PATH
.type = DRHD1_DEVSCOPE0_TYPE,
.id = DRHD1_DEVSCOPE0_ID,
.bus = DRHD1_DEVSCOPE0_BUS,
.devfun = DRHD1_DEVSCOPE0_PATH,
},
{
.type = DRHD1_DEVSCOPE1_TYPE,
.id = DRHD1_DEVSCOPE1_ID,
.bus = DRHD1_DEVSCOPE1_BUS,
.devfun = DRHD1_DEVSCOPE1_PATH
.type = DRHD1_DEVSCOPE1_TYPE,
.id = DRHD1_DEVSCOPE1_ID,
.bus = DRHD1_DEVSCOPE1_BUS,
.devfun = DRHD1_DEVSCOPE1_PATH,
},
};
static struct dmar_drhd drhd_info_array[DRHD_COUNT] = {
{
.dev_cnt = DRHD0_DEV_CNT,
.segment = DRHD0_SEGMENT,
.flags = DRHD0_FLAGS,
.dev_cnt = DRHD0_DEV_CNT,
.segment = DRHD0_SEGMENT,
.flags = DRHD0_FLAGS,
.reg_base_addr = DRHD0_REG_BASE,
.ignore = DRHD0_IGNORE,
.devices = drhd0_dev_scope
.ignore = DRHD0_IGNORE,
.devices = drhd0_dev_scope
},
{
.dev_cnt = DRHD1_DEV_CNT,
.segment = DRHD1_SEGMENT,
.flags = DRHD1_FLAGS,
.dev_cnt = DRHD1_DEV_CNT,
.segment = DRHD1_SEGMENT,
.flags = DRHD1_FLAGS,
.reg_base_addr = DRHD1_REG_BASE,
.ignore = DRHD1_IGNORE,
.devices = drhd1_dev_scope
.ignore = DRHD1_IGNORE,
.devices = drhd1_dev_scope
},
};
@ -59,9 +73,39 @@ struct dmar_info plat_dmar_info = {
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_mba_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
#endif
const struct cpu_state_table board_cpu_state_tbl;
static const struct cpu_cx_data board_cpu_cx[3] = {
{{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */
{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1816UL}, 0x02U, 0x97U, 0x00U}, /* C2 */
{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1819UL}, 0x03U, 0x40AU, 0x00U}, /* C3 */
};
static const struct cpu_px_data board_cpu_px[16] = {
{0x835UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002A00UL, 0x002A00UL}, /* P0 */
{0x834UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001500UL, 0x001500UL}, /* P1 */
{0x76CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x001300UL, 0x001300UL}, /* P2 */
{0x708UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001200UL, 0x001200UL}, /* P3 */
{0x6A4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001100UL, 0x001100UL}, /* P4 */
{0x640UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001000UL, 0x001000UL}, /* P5 */
{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P6 */
{0x578UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000E00UL, 0x000E00UL}, /* P7 */
{0x4B0UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000C00UL, 0x000C00UL}, /* P8 */
{0x44CUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000B00UL, 0x000B00UL}, /* P9 */
{0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P10 */
{0x320UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000800UL, 0x000800UL}, /* P11 */
{0x2BCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000700UL, 0x000700UL}, /* P12 */
{0x258UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000600UL, 0x000600UL}, /* P13 */
{0x1F4UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000500UL, 0x000500UL}, /* P14 */
{0x190UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000400UL, 0x000400UL}, /* P15 */
};
const struct cpu_state_table board_cpu_state_tbl = {
"Intel(R) Core(TM) i7-8650U CPU @ 1.90GHz",
{(uint8_t)ARRAY_SIZE(board_cpu_px), board_cpu_px,
(uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx}
};
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];

53
misc/vm_configs/boards/nuc7i7dnb/pci_devices.h
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@ -1,20 +1,61 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* BIOS Information
* Vendor: Intel Corp.
* Version: DNKBLi7v.86A.0065.2019.0611.1424
* Release Date: 06/11/2019
* BIOS Revision: 5.6
*
* Base Board Information
* Manufacturer: Intel Corporation
* Product Name: NUC7i7DNB
* Version: J83500-204
*/
#ifndef PCI_DEVICES_H_
#define PCI_DEVICES_H_
#define PTDEV_HI_MMIO_SIZE 0xe00000UL
#define HOST_BRIDGE .pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U}
#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U}
#define VGA_COMPATIBLE_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U}
#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}
#define SYSTEM_PERIPHERAL_0 .pbdf.bits = {.b = 0x00U, .d = 0x08U, .f = 0x00U}
#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1fU, .f = 0x06U}
#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}
#define NETWORK_CONTROLLER_0 .pbdf.bits = {.b = 0x01U, .d = 0x00U, .f = 0x00U}
#define SIGNAL_PROCESSING_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x02U}
#define SIGNAL_PROCESSING_CONTROLLER_1 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x00U}
#define SIGNAL_PROCESSING_CONTROLLER_2 .pbdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x01U}
#define COMMUNICATION_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x00U}
#define SERIAL_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x03U}
#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U}
#define PCI_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x00U}
#define PCI_BRIDGE_1 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x00U}
#define ISA_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x00U}
#define MEMORY_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x02U}
#define AUDIO_DEVICE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x03U}
#define SMBUS_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x04U}
#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x06U}
#define NETWORK_CONTROLLER_0 .pbdf.bits = {.b = 0x01U, .d = 0x00U, .f = 0x00U}
#define NON_VOLATILE_MEMORY_CONTROLLER_0 .pbdf.bits = {.b = 0x02U, .d = 0x00U, .f = 0x00U}
#endif /* PCI_DEVICES_H_ */

21
misc/vm_configs/boards/nuc7i7dnb/platform_acpi_info.h
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@ -1,16 +1,12 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* This is a template header file for nuc7i7dnb platform ACPI info definition
* works when Kconfig of ENFORCE_VALIDATED_ACPI_INFO is disabled.
* When ENFORCE_VALIDATED_ACPI_INFO is enabled, we should use
* ./misc/acrn-config/target/board_parser.py running on target
* to generate nuc7i7dnb specific acpi info file named as nuc7i7dnb_acpi_info.h
* and put it in hypervisor/arch/x86/configs/nuc7i7dnb/.
/* DO NOT MODIFY THIS FILE UNLESS YOU KNOW WHAT YOU ARE DOING!
*/
#ifndef PLATFORM_ACPI_INFO_H
#define PLATFORM_ACPI_INFO_H
@ -32,18 +28,14 @@
#define PM1A_EVT_ACCESS_SIZE 0x2U
#define PM1A_CNT_ADDRESS 0x1804UL
#define WAKE_VECTOR_32 0x7FA22F8CUL
#define WAKE_VECTOR_64 0x7FA22F98UL
#define WAKE_VECTOR_32 0x8AA09F8CUL
#define WAKE_VECTOR_64 0x8AA09F98UL
#define RESET_REGISTER_ADDRESS 0xCF9UL
#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
#define RESET_REGISTER_VALUE 0x6U
/* PCI mmcfg base of MCFG */
#define DEFAULT_PCI_MMCFG_BASE 0xE0000000UL
/* DRHD of DMAR */
#define DRHD_COUNT 2U
#define DRHD0_DEV_CNT 0x1U
@ -70,4 +62,7 @@
#define DRHD1_DEVSCOPE1_BUS 0x0U
#define DRHD1_DEVSCOPE1_PATH 0xf8U
/* PCI mmcfg base of MCFG */
#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL
#endif /* PLATFORM_ACPI_INFO_H */

22
misc/vm_configs/scenarios/hybrid/nuc7i7dnb/misc_cfg.h
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,20 +7,22 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#define ROOTFS_0 "root=/dev/sda3 "
#define ROOTFS_1 "root=/dev/nvme0n1p3 "
#define SOS_ROOTFS ROOTFS_0
#define SOS_ROOTFS "root=/dev/sda3 "
#define SOS_CONSOLE "console=ttyS0 "
#define SOS_COM1_BASE 0x3F8U
#define SOS_COM1_IRQ 4U
#define SOS_COM2_BASE 0x2F8U
#define SOS_COM2_IRQ 3U
#ifndef CONFIG_RELEASE
#define SOS_BOOTARGS_DIFF "hvlog=2M@0xE00000 memmap=0x200000$0xE00000 "
#else
#define SOS_BOOTARGS_DIFF ""
#endif
#define SOS_BOOTARGS_DIFF "rw " \
"rootwait " \
"console=tty0 " \
"consoleblank=0 " \
"no_timer_check " \
"quiet " \
"loglevel=3 " \
"i915.nuclear_pageflip=1 " \
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#endif /* MISC_CFG_H */

38
misc/vm_configs/scenarios/hybrid/nuc7i7dnb/nuc7i7dnb.config
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@ -1,5 +1,37 @@
# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)
# Board defconfig generated by acrn-config tool
CONFIG_BOARD="nuc7i7dnb"
CONFIG_SERIAL_LEGACY=y
CONFIG_HV_RAM_START=0x41000000
CONFIG_HV_RAM_START=0x11000000
CONFIG_HV_RAM_SIZE=0x9600000
CONFIG_PLATFORM_RAM_SIZE=0x400000000
CONFIG_LOW_RAM_SIZE=0x00010000
CONFIG_SOS_RAM_SIZE=0x400000000
CONFIG_UOS_RAM_SIZE=0x200000000
CONFIG_STACK_SIZE=0x2000
CONFIG_GPU_SBDF=0x00000010
CONFIG_UEFI_OS_LOADER_NAME=""
CONFIG_SCHED_BVT=y
CONFIG_RELOC=y
CONFIG_MULTIBOOT2=y
CONFIG_RDT_ENABLED=n
CONFIG_CDP_ENABLED=n
CONFIG_HYPERV_ENABLED=y
CONFIG_IOMMU_ENFORCE_SNP=n
CONFIG_ACPI_PARSE_ENABLED=y
CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n
CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n
CONFIG_IOMMU_BUS_NUM=0x100
CONFIG_MAX_IOAPIC_NUM=1
CONFIG_MAX_IR_ENTRIES=256
CONFIG_MAX_PCI_DEV_NUM=96
CONFIG_MAX_IOAPIC_LINES=120
CONFIG_MAX_PT_IRQ_ENTRIES=64
CONFIG_MAX_MSIX_TABLE_NUM=64
CONFIG_MAX_EMULATED_MMIO_REGIONS=16
CONFIG_SERIAL_LEGACY=y
CONFIG_SERIAL_PIO_BASE=0x3F8
CONFIG_LOG_BUF_SIZE=0x40000
CONFIG_NPK_LOGLEVEL_DEFAULT=5
CONFIG_MEM_LOGLEVEL_DEFAULT=5
CONFIG_LOG_DESTINATION=7
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3

12
misc/vm_configs/scenarios/hybrid/nuc7i7dnb/pci_dev.c Normal file
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@ -0,0 +1,12 @@
/*
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <pci_devices.h>
#include <vpci.h>
#include <vbar_base.h>
#include <mmu.h>
#include <page.h>

44
misc/vm_configs/scenarios/hybrid/nuc7i7dnb/vbar_base.h Normal file
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@ -0,0 +1,44 @@
/*
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VBAR_BASE_H_
#define VBAR_BASE_H_
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0xde000000UL, \
.vbar_base[2] = 0xc0000000UL
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0xdf252000UL
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf230000UL
#define SIGNAL_PROCESSING_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf251000UL
#define SIGNAL_PROCESSING_CONTROLLER_1_VBAR .vbar_base[0] = 0xdf250000UL
#define SIGNAL_PROCESSING_CONTROLLER_2_VBAR .vbar_base[0] = 0xdf24f000UL
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf24e000UL
#define SERIAL_CONTROLLER_0_VBAR .vbar_base[1] = 0xdf24d000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf248000UL, \
.vbar_base[1] = 0xdf24c000UL, \
.vbar_base[5] = 0xdf24b000UL
#define MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf244000UL
#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = 0xdf240000UL, \
.vbar_base[4] = 0xdf220000UL
#define SMBUS_0_VBAR .vbar_base[0] = 0xdf24a000UL
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf200000UL
#define NETWORK_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf100000UL
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0xdf000000UL
#endif /* VBAR_BASE_H_ */

22
misc/vm_configs/scenarios/hybrid/vm_configurations.c
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@ -1,9 +1,8 @@
/*
* Copyright (C) 2018 Intel Corporation. All rights reserved.
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <vuart.h>
#include <pci_dev.h>
@ -12,17 +11,18 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
{ /* VM0 */
CONFIG_SAFETY_VM(1),
.name = "ACRN PRE-LAUNCHED VM0",
.guest_flags = 0UL,
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
.guest_flags = 0UL,
.memory = {
.start_hpa = VM0_CONFIG_MEM_START_HPA,
.size = VM0_CONFIG_MEM_SIZE,
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
},
.os_config = {
.name = "Zephyr",
.kernel_type = KERNEL_ZEPHYR,
.kernel_mod_tag = "Zephyr_RawImage",
.bootargs = "",
.kernel_load_addr = 0x100000,
.kernel_entry_addr = 0x100000,
},
@ -38,18 +38,12 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.t_vuart.vm_id = 1U,
.t_vuart.vuart_id = 1U,
},
#ifdef VM0_PASSTHROUGH_TPM
.pt_tpm2 = true,
.mmiodevs[0] = {
.base_gpa = VM0_TPM_BUFFER_BASE_ADDR,
.base_hpa = 0xFED40000UL,
.size = VM0_TPM_BUFFER_SIZE,
},
#endif
},
{ /* VM1 */
CONFIG_SOS_VM,
.name = "ACRN SOS VM",
/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
.guest_flags = 0UL,
.memory = {
.start_hpa = 0UL,
@ -85,6 +79,6 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
}
}
},
},
};

35
misc/vm_configs/scenarios/hybrid/vm_configurations.h
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@ -1,17 +1,13 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VM_CONFIGURATIONS_H
#define VM_CONFIGURATIONS_H
#include <misc_cfg.h>
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
#include <pci_devices.h>
/* SOS_VM_NUM can only be 0U or 1U;
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
@ -22,23 +18,22 @@
#define MAX_POST_VM_NUM 1U
#define CONFIG_MAX_KATA_VM_NUM 0U
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(3U))
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(3U))
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
#define VM0_CONFIG_PCI_DEV_NUM 1U
#define SOS_VM_BOOTARGS SOS_ROOTFS \
"rw rootwait " \
"console=tty0 " \
SOS_CONSOLE \
"consoleblank=0 " \
"no_timer_check " \
"quiet loglevel=3 " \
"i915.nuclear_pageflip=1 " \
"i915.avail_planes_per_pipe=0x010700 " \
"i915.domain_plane_owners=0x011100001111 " \
"i915.enable_gvt=1 " \
SOS_IDLE \
SOS_IDLE \
SOS_BOOTARGS_DIFF
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U))
#endif /* VM_CONFIGURATIONS_H */

22
misc/vm_configs/scenarios/industry/nuc7i7dnb/misc_cfg.h
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,20 +7,22 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#define ROOTFS_0 "root=/dev/sda3 "
#define ROOTFS_1 "root=/dev/nvme0n1p3 "
#define SOS_ROOTFS ROOTFS_0
#define SOS_ROOTFS "root=/dev/sda3 "
#define SOS_CONSOLE "console=ttyS0 "
#define SOS_COM1_BASE 0x3F8U
#define SOS_COM1_IRQ 4U
#define SOS_COM2_BASE 0x2F8U
#define SOS_COM2_IRQ 3U
#ifndef CONFIG_RELEASE
#define SOS_BOOTARGS_DIFF "hvlog=2M@0xE00000 memmap=0x200000$0xE00000 "
#else
#define SOS_BOOTARGS_DIFF ""
#endif
#define SOS_BOOTARGS_DIFF "rw " \
"rootwait " \
"console=tty0 " \
"consoleblank=0 " \
"no_timer_check " \
"quiet " \
"loglevel=3 " \
"i915.nuclear_pageflip=1 " \
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#endif /* MISC_CFG_H */

38
misc/vm_configs/scenarios/industry/nuc7i7dnb/nuc7i7dnb.config
View File

@ -1,5 +1,37 @@
# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)
# Board defconfig generated by acrn-config tool
CONFIG_BOARD="nuc7i7dnb"
CONFIG_SERIAL_LEGACY=y
CONFIG_HV_RAM_START=0x41000000
CONFIG_HV_RAM_START=0x11000000
CONFIG_HV_RAM_SIZE=0x14800000
CONFIG_PLATFORM_RAM_SIZE=0x400000000
CONFIG_LOW_RAM_SIZE=0x00010000
CONFIG_SOS_RAM_SIZE=0x400000000
CONFIG_UOS_RAM_SIZE=0x200000000
CONFIG_STACK_SIZE=0x2000
CONFIG_GPU_SBDF=0x00000010
CONFIG_UEFI_OS_LOADER_NAME="\\EFI\\BOOT\\bootx64.efi"
CONFIG_SCHED_BVT=y
CONFIG_RELOC=y
CONFIG_MULTIBOOT2=y
CONFIG_RDT_ENABLED=n
CONFIG_CDP_ENABLED=n
CONFIG_HYPERV_ENABLED=y
CONFIG_IOMMU_ENFORCE_SNP=n
CONFIG_ACPI_PARSE_ENABLED=y
CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n
CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n
CONFIG_IOMMU_BUS_NUM=0x100
CONFIG_MAX_IOAPIC_NUM=1
CONFIG_MAX_IR_ENTRIES=256
CONFIG_MAX_PCI_DEV_NUM=96
CONFIG_MAX_IOAPIC_LINES=120
CONFIG_MAX_PT_IRQ_ENTRIES=64
CONFIG_MAX_MSIX_TABLE_NUM=64
CONFIG_MAX_EMULATED_MMIO_REGIONS=16
CONFIG_SERIAL_LEGACY=y
CONFIG_SERIAL_PIO_BASE=0x3F8
CONFIG_LOG_BUF_SIZE=0x40000
CONFIG_NPK_LOGLEVEL_DEFAULT=5
CONFIG_MEM_LOGLEVEL_DEFAULT=5
CONFIG_LOG_DESTINATION=7
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3

12
misc/vm_configs/scenarios/industry/nuc7i7dnb/pci_dev.c Normal file
View File

@ -0,0 +1,12 @@
/*
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <pci_devices.h>
#include <vpci.h>
#include <vbar_base.h>
#include <mmu.h>
#include <page.h>

10
misc/vm_configs/scenarios/industry/nuc7i7dnb/vbar_base.h Normal file
View File

@ -0,0 +1,10 @@
/*
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VBAR_BASE_H_
#define VBAR_BASE_H_
#endif /* VBAR_BASE_H_ */

24
misc/vm_configs/scenarios/industry/vm_configurations.c
View File

@ -1,9 +1,8 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <vuart.h>
#include <pci_dev.h>
@ -12,8 +11,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
{ /* VM0 */
CONFIG_SOS_VM,
.name = "ACRN SOS VM",
/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
.guest_flags = 0UL,
.clos = { 0U },
.memory = {
.start_hpa = 0UL,
.size = CONFIG_SOS_RAM_SIZE,
@ -22,7 +22,7 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.name = "ACRN Service OS",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.bootargs = SOS_VM_BOOTARGS
.bootargs = SOS_VM_BOOTARGS,
},
.vuart[0] = {
.type = VUART_LEGACY_PIO,
@ -48,11 +48,10 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
}
},
},
{ /* VM2 */
CONFIG_POST_RT_VM(1),
.guest_flags = 0UL,
.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.type = VUART_LEGACY_PIO,
@ -78,7 +77,7 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
}
},
},
{ /* VM4 */
CONFIG_POST_STD_VM(3),
@ -91,7 +90,7 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
}
},
},
{ /* VM5 */
CONFIG_POST_STD_VM(4),
@ -104,7 +103,7 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
}
},
},
{ /* VM6 */
CONFIG_POST_STD_VM(5),
@ -117,19 +116,18 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
}
},
},
{ /* VM7 */
CONFIG_KATA_VM(1),
.cpu_affinity = VM7_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
.addr.port_base = INVALID_COM_BASE,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
}
},
},
};

31
misc/vm_configs/scenarios/industry/vm_configurations.h
View File

@ -1,13 +1,13 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VM_CONFIGURATIONS_H
#define VM_CONFIGURATIONS_H
#include <misc_cfg.h>
#include <pci_devices.h>
/* SOS_VM_NUM can only be 0U or 1U;
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
@ -19,29 +19,20 @@
#define CONFIG_MAX_KATA_VM_NUM 1U
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
#define SOS_VM_BOOTARGS SOS_ROOTFS \
"rw rootwait " \
"console=tty0 " \
SOS_CONSOLE \
"consoleblank=0 " \
"no_timer_check " \
"quiet loglevel=3 " \
"i915.nuclear_pageflip=1 " \
"i915.avail_planes_per_pipe=0x01010F " \
"i915.domain_plane_owners=0x011111110000 " \
"i915.enable_gvt=1 " \
SOS_IDLE \
SOS_IDLE \
SOS_BOOTARGS_DIFF
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM4_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM5_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM6_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM4_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM5_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM6_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#endif /* VM_CONFIGURATIONS_H */

3
misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/misc_cfg.h
View File

@ -7,7 +7,4 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#define ROOTFS_0 "root=/dev/sda3 "
#define ROOTFS_1 "root=/dev/nvme0n1p3 "
#endif /* MISC_CFG_H */

38
misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/nuc7i7dnb.config
View File

@ -1,5 +1,37 @@
# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)
# Board defconfig generated by acrn-config tool
CONFIG_BOARD="nuc7i7dnb"
CONFIG_SERIAL_LEGACY=y
CONFIG_HV_RAM_START=0x41000000
CONFIG_HV_RAM_START=0x11000000
CONFIG_HV_RAM_SIZE=0x7800000
CONFIG_PLATFORM_RAM_SIZE=0x400000000
CONFIG_LOW_RAM_SIZE=0x00010000
CONFIG_SOS_RAM_SIZE=0x400000000
CONFIG_UOS_RAM_SIZE=0x200000000
CONFIG_STACK_SIZE=0x2000
CONFIG_GPU_SBDF=0x00000010
CONFIG_UEFI_OS_LOADER_NAME=""
CONFIG_SCHED_BVT=y
CONFIG_RELOC=y
CONFIG_MULTIBOOT2=y
CONFIG_RDT_ENABLED=n
CONFIG_CDP_ENABLED=n
CONFIG_HYPERV_ENABLED=y
CONFIG_IOMMU_ENFORCE_SNP=n
CONFIG_ACPI_PARSE_ENABLED=y
CONFIG_L1D_FLUSH_VMENTRY_ENABLED=n
CONFIG_MCE_ON_PSC_WORKAROUND_DISABLED=n
CONFIG_IOMMU_BUS_NUM=0x100
CONFIG_MAX_IOAPIC_NUM=1
CONFIG_MAX_IR_ENTRIES=256
CONFIG_MAX_PCI_DEV_NUM=96
CONFIG_MAX_IOAPIC_LINES=120
CONFIG_MAX_PT_IRQ_ENTRIES=64
CONFIG_MAX_MSIX_TABLE_NUM=64
CONFIG_MAX_EMULATED_MMIO_REGIONS=16
CONFIG_SERIAL_LEGACY=y
CONFIG_SERIAL_PIO_BASE=0x3F8
CONFIG_LOG_BUF_SIZE=0x40000
CONFIG_NPK_LOGLEVEL_DEFAULT=5
CONFIG_MEM_LOGLEVEL_DEFAULT=5
CONFIG_LOG_DESTINATION=7
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=3

2
misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/pci_dev.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

32
misc/vm_configs/scenarios/logical_partition/vm_configurations.c
View File

@ -1,11 +1,11 @@
/*
* Copyright (C) 2018 Intel Corporation. All rights reserved.
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <vuart.h>
#include <pci_dev.h>
extern struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM];
extern struct acrn_vm_pci_dev_config vm1_pci_devs[VM1_CONFIG_PCI_DEV_NUM];
@ -15,20 +15,20 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
CONFIG_PRE_STD_VM(1),
.name = "ACRN PRE-LAUNCHED VM0",
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
.guest_flags = 0UL,
.memory = {
.start_hpa = VM0_CONFIG_MEM_START_HPA,
.size = VM0_CONFIG_MEM_SIZE,
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
},
.os_config = {
.name = "ClearLinux",
.name = "YOCTO",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.bootargs = VM0_CONFIG_OS_BOOTARG_CONSOLE \
VM0_CONFIG_OS_BOOTARG_MAXCPUS \
VM0_CONFIG_OS_BOOTARG_ROOT \
"rw rootwait noxsave nohpet \
no_timer_check ignore_loglevel log_buf_len=16M \
consoleblank=0 tsc=reliable"
.bootargs = "rw rootwait root=/dev/sda3 console=ttyS0 \
noxsave nohpet no_timer_check ignore_loglevel \
log_buf_len=16M consoleblank=0 tsc=reliable "
},
.vuart[0] = {
.type = VUART_LEGACY_PIO,
@ -49,21 +49,19 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
CONFIG_PRE_STD_VM(2),
.name = "ACRN PRE-LAUNCHED VM1",
.cpu_affinity = VM1_CONFIG_CPU_AFFINITY,
.guest_flags = (GUEST_FLAG_RT | GUEST_FLAG_LAPIC_PASSTHROUGH),
.memory = {
.start_hpa = VM1_CONFIG_MEM_START_HPA,
.size = VM1_CONFIG_MEM_SIZE,
.start_hpa2 = VM1_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM1_CONFIG_MEM_SIZE_HPA2,
},
.os_config = {
.name = "ClearLinux",
.name = "YOCTO",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.bootargs = VM1_CONFIG_OS_BOOTARG_CONSOLE \
VM1_CONFIG_OS_BOOTARG_MAXCPUS \
VM1_CONFIG_OS_BOOTARG_ROOT \
"rw rootwait noxsave nohpet \
no_timer_check ignore_loglevel log_buf_len=16M \
consoleblank=0 tsc=reliable"
.bootargs = "rw rootwait root=/dev/sda3 console=ttyS0 \
noxsave nohpet no_timer_check ignore_loglevel \
log_buf_len=16M consoleblank=0 tsc=reliable "
},
.vuart[0] = {
.type = VUART_LEGACY_PIO,

66
misc/vm_configs/scenarios/logical_partition/vm_configurations.h
View File

@ -1,17 +1,13 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
* Copyright (C) 2020 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VM_CONFIGURATIONS_H
#define VM_CONFIGURATIONS_H
#include <pci_devices.h>
#include <misc_cfg.h>
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
#define DM_OWNED_GUEST_FLAG_MASK 0UL
#include <pci_devices.h>
/* SOS_VM_NUM can only be 0U or 1U;
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
@ -22,52 +18,20 @@
#define MAX_POST_VM_NUM 0U
#define CONFIG_MAX_KATA_VM_NUM 0U
/* The VM CONFIGs like:
* VMX_CONFIG_CPU_AFFINITY
* VMX_CONFIG_MEM_START_HPA
* VMX_CONFIG_MEM_SIZE
* VMX_CONFIG_OS_BOOTARG_ROOT
* VMX_CONFIG_OS_BOOTARG_MAX_CPUS
* VMX_CONFIG_OS_BOOTARG_CONSOLE
* might be different on your board, please modify them per your needs.
*/
#define DM_OWNED_GUEST_FLAG_MASK 0UL
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(2U))
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
#define VM0_CONFIG_OS_BOOTARG_ROOT ROOTFS_0
#define VM0_CONFIG_OS_BOOTARG_MAXCPUS "maxcpus=2 "
#define VM0_CONFIG_OS_BOOTARG_CONSOLE "console=ttyS0 "
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(2U))
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
#define VM0_CONFIG_PCI_DEV_NUM 3U
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U))
#define VM1_CONFIG_MEM_START_HPA 0x120000000UL
#define VM1_CONFIG_MEM_SIZE 0x20000000UL
#define VM1_CONFIG_OS_BOOTARG_ROOT ROOTFS_0
#define VM1_CONFIG_OS_BOOTARG_MAXCPUS "maxcpus=2 "
#define VM1_CONFIG_OS_BOOTARG_CONSOLE "console=ttyS0 "
/* VM pass-through devices assign policy:
* VM0: one Mass Storage controller, one Network controller;
* VM1: one Mass Storage controller, one Network controller(if a secondary Network controller class device exist);
*/
#define VM0_STORAGE_CONTROLLER SATA_CONTROLLER_0
#define VM0_NETWORK_CONTROLLER ETHERNET_CONTROLLER_0
#define VM0_CONFIG_PCI_DEV_NUM 3U
#define VM1_STORAGE_CONTROLLER USB_CONTROLLER_0
#if defined(ETHERNET_CONTROLLER_1)
/* if a secondary Ethernet controller subclass exist, assign to VM1 */
#define VM1_NETWORK_CONTROLLER ETHERNET_CONTROLLER_1
#elif defined(NETWORK_CONTROLLER_0)
/* if a Network controller subclass exist(usually it is a wireless network card), assign to VM1 */
#define VM1_NETWORK_CONTROLLER NETWORK_CONTROLLER_0
#endif
#if defined(VM1_NETWORK_CONTROLLER)
#define VM1_CONFIG_PCI_DEV_NUM 3U
#else
/* no network controller could be assigned to VM1 */
#define VM1_CONFIG_PCI_DEV_NUM 2U
#endif
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U))
#define VM1_CONFIG_MEM_START_HPA 0x120000000UL
#define VM1_CONFIG_MEM_SIZE 0x20000000UL
#define VM1_CONFIG_MEM_START_HPA2 0x0UL
#define VM1_CONFIG_MEM_SIZE_HPA2 0x0UL
#define VM1_CONFIG_PCI_DEV_NUM 3U
#endif /* VM_CONFIGURATIONS_H */