hv: config: add msix emulation support

The information needed to enable MSI-x emulation.
Only enable MSI-x emuation for the devices in msix_emul_devs array.
Currently, only EHL has the need to enable MSI-x emulation for TSN
devices.

Tracked-On: #4831
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

hypervisor/arch/x86/configs/apl-mrb/board.c

@@ -30,3 +30,4 @@ const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM] = {
                .bits.f = 0x0U,
        },
 };
+const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];

hypervisor/arch/x86/configs/apl-mrb/misc_cfg.h

@@ -9,6 +9,7 @@
 
 #define MAX_PCPU_NUM	4U
 #define MAX_PLATFORM_CLOS_NUM	0U
+#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U
 
 #define ROOTFS_0		"root=/dev/sda3 "
 #define ROOTFS_1		"root=/dev/mmcblk1p1 "

hypervisor/arch/x86/configs/apl-up2/board.c

@@ -48,3 +48,4 @@ const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM] = {
 		.bits.f = 0x0,
 	},
 };
+const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];

hypervisor/arch/x86/configs/apl-up2/misc_cfg.h

@@ -9,6 +9,7 @@
 
 #define MAX_PCPU_NUM	4U
 #define MAX_PLATFORM_CLOS_NUM	4U
+#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U
 
 #define ROOTFS_0		"root=/dev/sda3 "
 #define ROOTFS_1		"root=/dev/mmcblk0p3 "

hypervisor/arch/x86/configs/dnv-cb2/board.c

@@ -23,3 +23,4 @@ struct platform_clos_info platform_mba_clos_array[MAX_PLATFORM_CLOS_NUM];
 
 const struct cpu_state_table board_cpu_state_tbl;
 const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
+const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];

hypervisor/arch/x86/configs/dnv-cb2/misc_cfg.h

@@ -9,6 +9,7 @@
 
 #define MAX_PCPU_NUM	8U
 #define MAX_PLATFORM_CLOS_NUM	0U
+#define MAX_VMSIX_ON_MSI_PDEVS_NUM	0U
 
 #define ROOTFS_0		"root=/dev/sda3 "
 

hypervisor/arch/x86/configs/generic/board.c

@@ -23,3 +23,4 @@ struct platform_clos_info platform_mba_clos_array[MAX_PLATFORM_CLOS_NUM];
 
 const struct cpu_state_table board_cpu_state_tbl;
 const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
+const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];

hypervisor/arch/x86/configs/generic/misc_cfg.h

@@ -9,6 +9,7 @@
 
 #define MAX_PCPU_NUM	4U
 #define MAX_PLATFORM_CLOS_NUM	0U
+#define MAX_VMSIX_ON_MSI_PDEVS_NUM	0U
 
 #define ROOTFS_0		"root=/dev/sda3 "
 #define ROOTFS_1		"root=/dev/mmcblk0p1 "

hypervisor/arch/x86/configs/icl-rvp/board.c

@@ -23,3 +23,4 @@ struct platform_clos_info platform_mba_clos_array[MAX_PLATFORM_CLOS_NUM];
 
 const struct cpu_state_table board_cpu_state_tbl;
 const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
+const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];

hypervisor/arch/x86/configs/nuc6cayh/board.c

@@ -23,3 +23,4 @@ struct platform_clos_info platform_mba_clos_array[MAX_PLATFORM_CLOS_NUM];
 
 const struct cpu_state_table board_cpu_state_tbl;
 const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
+const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];

hypervisor/arch/x86/configs/nuc6cayh/misc_cfg.h

@@ -9,6 +9,7 @@
 
 #define MAX_PCPU_NUM	4U
 #define MAX_PLATFORM_CLOS_NUM	0U
+#define MAX_VMSIX_ON_MSI_PDEVS_NUM	0U
 
 #define ROOTFS_0		"root=/dev/sda3 "
 

hypervisor/arch/x86/configs/nuc7i7dnb/board.c

@@ -64,3 +64,4 @@ struct platform_clos_info platform_mba_clos_array[MAX_PLATFORM_CLOS_NUM];
 
 const struct cpu_state_table board_cpu_state_tbl;
 const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
+const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];

hypervisor/arch/x86/configs/nuc7i7dnb/misc_cfg.h

@@ -9,6 +9,7 @@
 
 #define MAX_PCPU_NUM	4U
 #define MAX_PLATFORM_CLOS_NUM	0U
+#define MAX_VMSIX_ON_MSI_PDEVS_NUM	0U
 
 #define ROOTFS_0		"root=/dev/sda3 "
 #define ROOTFS_1		"root=/dev/nvme0n1p3 "

hypervisor/arch/x86/configs/whl-ipc-i5/board.c

@@ -96,3 +96,4 @@ const struct cpu_state_table board_cpu_state_tbl = {
 	(uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx}
 };
 const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
+const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];

hypervisor/arch/x86/configs/whl-ipc-i5/misc_cfg.h

@@ -10,6 +10,7 @@
 
 #define MAX_PCPU_NUM		4U
 #define MAX_PLATFORM_CLOS_NUM	0U
+#define MAX_VMSIX_ON_MSI_PDEVS_NUM	0U
 
 #define ROOTFS_0		"root=/dev/nvme0n1p3 "
 #define ROOTFS_1		"root=/dev/sda3 "

hypervisor/include/arch/x86/board.h

@@ -20,6 +20,11 @@ struct platform_clos_info {
 	uint32_t msr_index;
 };
 
+struct vmsix_on_msi_info {
+	union pci_bdf bdf;
+	uint64_t mmio_base;
+};
+
 extern struct dmar_info plat_dmar_info;
 
 #ifdef CONFIG_RDT_ENABLED
@@ -30,5 +35,6 @@ extern struct platform_clos_info platform_mba_clos_array[MAX_PLATFORM_CLOS_NUM];
 
 extern const struct cpu_state_table board_cpu_state_tbl;
 extern const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
+extern const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];
 
 #endif /* BOARD_H */