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c907a820df
The information needed to enable MSI-x emulation. Only enable MSI-x emuation for the devices in msix_emul_devs array. Currently, only EHL has the need to enable MSI-x emulation for TSN devices. Tracked-On: #4831 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
47 lines
1022 B
C
47 lines
1022 B
C
/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MISC_CFG_H
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#define MISC_CFG_H
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#define MAX_PCPU_NUM 4U
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#define MAX_PLATFORM_CLOS_NUM 4U
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#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U
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#define ROOTFS_0 "root=/dev/sda3 "
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#define ROOTFS_1 "root=/dev/mmcblk0p3 "
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#define SOS_ROOTFS ROOTFS_1
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#define SOS_CONSOLE "console=ttyS0 "
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#define SOS_COM1_BASE 0x3F8U
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#define SOS_COM1_IRQ 4U
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#define SOS_COM2_BASE 0x2F8U
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#define SOS_COM2_IRQ 3U
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#ifndef CONFIG_RELEASE
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#define BOOTARG_DEBUG "hvlog=2M@0xe00000 " \
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"memmap=0x600000$0xa00000 " \
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"ramoops.mem_address=0xa00000 " \
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"ramoops.mem_size=0x400000 " \
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"ramoops.console_size=0x200000 " \
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"reboot_panic=p,w "
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#else
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#define BOOTARG_DEBUG ""
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#endif
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#define SOS_BOOTARGS_DIFF BOOTARG_DEBUG \
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"module_blacklist=dwc3_pci " \
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"i915.enable_guc=0x02 " \
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"cma=64M@0- "
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#define MAX_HIDDEN_PDEVS_NUM 1U
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#define HI_MMIO_START ~0UL
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#define HI_MMIO_END 0UL
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#endif /* MISC_CFG_H */
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